News & Analysis
ISSCC preview: Revving ReRAMS, boosting memory bandwidth
Brian Fuller
11/19/2012 9:05 AM EST
Sizzling SRAM; bandwidth busters
"ReRAM now has the opportunity to be adopted as a storage-class memory competing with the existing NAND Flash memories for nonvolatile mass storage applications," the paper's presenters argue.
Another ReRAM paper, from Panasonic, presents an ReRAM filament-scaling forming technique and level-verify-write scheme with endurance over 107 cycles for a 16nm cell. It is realized within a 1T1R ReRAM array.
SRAM advances
On the SRAM front, designers continue to struggle with leakage and dynamic power reductions as process nodes dive down past 45nm. The use of "FinFETS and fully-depleted SOI are key to enabling the continuous scaling of bit cell area and low voltage performance" at 22nm and below, Zhang notes.
TSMC will present a paper describing the first 112Mb 6T SRAM at 20nm. It's the smallest known 6T-SRAM bit cell area at 0.081μm2. A four-state power-management scheme reduces retention leakage by over 65%.
Bandwidth busters
Memory bandwidth continues to advance this conference with one of the highest reported data rates for memory transceivers. Rambus will describe a single-ended transceiver design with a 6.4Gb/s/pin for high-density dual-rank DIMM modules. At the 2012 ISSCC, Rambus presented a paper for a similar technology but at half the speed (3.2Gb/s/pin DDR4). T he devicealso achieves exceptional power efficiency at 9.1mW/Gb/s, which is essential for future applications.
"This design has demonstrated the potential to be used in various VLSI systems, including data center servers, networking, and low-power handheld devices," Rambus writes in a paper preview. "The design should enable significant boost in performance due to higher data rate while keeping the overall DRAM power consumption at minimum."
For more information, please visit the ISSCC site.
"ReRAM now has the opportunity to be adopted as a storage-class memory competing with the existing NAND Flash memories for nonvolatile mass storage applications," the paper's presenters argue.
Another ReRAM paper, from Panasonic, presents an ReRAM filament-scaling forming technique and level-verify-write scheme with endurance over 107 cycles for a 16nm cell. It is realized within a 1T1R ReRAM array.
SRAM advances
On the SRAM front, designers continue to struggle with leakage and dynamic power reductions as process nodes dive down past 45nm. The use of "FinFETS and fully-depleted SOI are key to enabling the continuous scaling of bit cell area and low voltage performance" at 22nm and below, Zhang notes.
TSMC will present a paper describing the first 112Mb 6T SRAM at 20nm. It's the smallest known 6T-SRAM bit cell area at 0.081μm2. A four-state power-management scheme reduces retention leakage by over 65%.
Bandwidth busters
Memory bandwidth continues to advance this conference with one of the highest reported data rates for memory transceivers. Rambus will describe a single-ended transceiver design with a 6.4Gb/s/pin for high-density dual-rank DIMM modules. At the 2012 ISSCC, Rambus presented a paper for a similar technology but at half the speed (3.2Gb/s/pin DDR4). T he devicealso achieves exceptional power efficiency at 9.1mW/Gb/s, which is essential for future applications.
DRAM data rate/pin trends
"This design has demonstrated the potential to be used in various VLSI systems, including data center servers, networking, and low-power handheld devices," Rambus writes in a paper preview. "The design should enable significant boost in performance due to higher data rate while keeping the overall DRAM power consumption at minimum."
For more information, please visit the ISSCC site.
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John_Galt
11/20/2012 10:30 AM EST
I would be interesting to see cost-per-bit targets for the various non-volatile technologies.
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resistion
11/20/2012 8:18 PM EST
Brian, is your information from a press kit? Is it publicly available? I could not view abstracts from the advance program. Thanks.
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Brian Fuller2
11/21/2012 10:22 AM EST
@resistion, here's a link to the advanced program:
http://www.miracd.com/ISSCC2013/PDF/ISSCC2013AdvanceProgram.pdf
I'll see if I can get access for the press materials for you folks, which has some more detail but is gated right now.
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kjdsfkjdshfkdshfvc
11/22/2012 7:54 AM EST
its just a comment you understand but theres something very wrong here, it seems all these are test chips fresh out the lab, now thats good.
don't get me wrong, but people are fed up now always hearing whats perpetually always in the lad or test chip, and for no other reason than its here "last year’s ISSCC is 64Mb for ReRAM and 8Gb for PRAM"
theres also mention of smaller future processes and how thats good 16nm,22nm,24nm etc
however where are the commercial products Today, and why didn't F RAM get a mention here ?
or Especially Mram gets only "making steady progress towards product introductions..." when
http://semiaccurate.com/2012/11/16/everspin-makes-st-mram-a-reality/
after talking with everspin on the phone directly states something far better , it's commercially available "NOW", "The ST-MRAM shown today is built on a standard 90nm process, and from that you get a 64Mb chip that is pin compatible with a DDR3 DRAM."
"Current DDR3 controllers, if they follow the spec fully, should be able to work with ST-MRAM."
"Looking forward a bit, if you can get 64Mb chips out of a 90nm process, think about what happens when you move to a modern process. Process"
and he finishes with best of all
"Impending shrinks mean ST-MRAM has a pretty good outlook. Once this technology goes mainstream it will change things, count on it.S|A"
so all told, finally we get this new (well old given Freescale commercialized oddball versions of this 2004 before passing it to everspin) fast as current Dram packages, in a cheap and generic 90nm process with lots of very quick progression to something even better Now, today,in stock,commercially,and so retail real soon now (in the real meaning of the end user word...)
like i said only wanted to make a comment, sorry for the tangent but you and everyone should be screaming this from all the front pages so people buy...
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resistion
11/24/2012 10:35 AM EST
But why would commercialized stuff, already well-researched, be talked about at research conferences?
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resistion
11/24/2012 10:40 AM EST
If MRAM or FRAM want to grow their niches, research might be the last thing they want to associate with.
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kjdsfkjdshfkdshfvc
11/25/2012 10:45 AM EST
i don't know perhaps the same reason antiquated limited write NAND Flash is still being researched
and talked about at research conferences?
and OC i don't recall it being said saying anything about it being "well-researched" only that its now a commercial product in a form people might use generally.
just because a produce is commercialized doesn't stop it being researched to bring improvements,NAND Flash proves that.
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resistion
11/25/2012 1:11 PM EST
NAND is commercialized, so any talk at the conference is only leading to its demise. However, it is so entrenched, it doesn't need growth, and its demise won't happen overnight. On the other hand, exposing faults of MRAM or FRAM could severely limit their ability to grow their markets, right now.
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kjdsfkjdshfkdshfvc
11/22/2012 8:24 AM EST
and not to take focus away from MRAM above, theres also the news that samsung just made a 64GB embedded multimedia card (eMMC) using [10nm]-class process technology to also consider http://www.digitimes.com/news/a20121116PR206.html
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kjdsfkjdshfkdshfvc
11/22/2012 8:29 AM EST
and by that i mean everyone knows antiquated "limited write" NAND Flash SSDs are reaching their limits already and wont go much past their current speeds , its time to transition and everyone put cash into Mram and move move over until the other stuffs finally out the Lab and on the shelfs for real.
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resistion
3/14/2013 12:20 PM EDT
It's always been a fundamental question, in a multi-layered memory, with the peripheral portion taking up more and more area, perhaps even initially exceeding the array area, doesn't the cost/bit reduction from additional layers quickly reach its limit, making it questionable to say it extends scalability?
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