Intel to detail tri-gate advances at IEDM
12/6/2012 10:01 AM EST
SAN FRANCISCO--A wild technical world of self-healing memories,
brain-like electronic systems, spintronics advances,
logic-on-plastic, and bio-integrated electronics unfolds next week
when the leading lights of semiconductor research parachute in here
for the annual International Electron Devices Meeting (IEDM).
The 58th annual IEDM includes a strong overall emphasis on
circuit-device interaction, energy harvesting and power devices, and
biomedical devices, spiced with intriguing keynotes from Samsung
(state of the art in displays), IMEC (ultimate device technologies)
and the University of Illinois (bio-integrated electronics).
Luncheon speakers include GlobalFoundries CEO Ajit Manocha ("Is the
fabless model dead?") and Marvell co-founder Weili Dai.
descriptions of tri-gate advances from Intel and 22-nm
silicon-on-insulator technology from IBM, as well as germanium
integrated directly on silicon in FinFETs (TSMC) are on the agenda.
What follows is a selection of paper highlights that will be
presented during the Monday-Wednesday sessions at the San Francisco
Hilton Hotel (and
a link to the IEDM technical program):
Neuromorphic--or brain-like--electronic systems that mimic cognitive
functions are the focus of research because of their potential for
complex tasks such as pattern-recognition. A technical
presentation by a team from Korea’s Gwangju Institute of Science
and Technology will detail a high-speed pattern-recognition system
comprising CMOS “neurons” and an array of resistive-RAM (RRAM)-based
“synapses,” which demonstrated something called
spike-timing-dependent plasticity (STDP). STDP is an electronic
analog of a brain mechanism for learning and memory, so an
electronic system that accurately performs STDP can be said to be
“learning.” The 1-Kb RRAM array has a simple crosspoint structure
and possibly can be scaled to 4F, the theoretical minimum size
for a crosspoint array.
(Paper #10.2, “RRAM-Based Synapse for Neuromorphic System with
Pattern-Recognition Function,” S. Park et al, Gwangju Institute of
Science and Technology)
A team led by Korea’s Gwangju Institute of Science and Technology will detail a high-speed pattern-recognition system comprising CMOS “neurons” and an array of resistive-RAM (RRAM)-based “synapses.”