News & Analysis
Intel to detail tri-gate advances at IEDM
Nicolas Mokhoff, Brian Fuller
12/6/2012 10:01 AM EST
The next big thing?
Graphene is the next big thing in device science and has been for many years now, the old joke goes. It's thin, carbon-based and offers high current density and electron mobility. IEDM will dedicate session 4 (Monday, 1:30 p.m. PST) to graphene and low-dimensional nano device technology.
But there may be a new sheriff in graphene town: Molybdenum Sulfide (MoS). Possessing some characteristics similar to graphene, MoS also claims a wide energy bandgap, enabling transistors and circuits to be built from it directly. An M.I.T.-led team will describe the use of CVD processing to grow uniform, flexible, single-molecular layers of MoS, comprising a layer of Mo atoms sandwiched between two layers of S atoms. They exploited the material’s 1.8 eV bandgap to build MoS transistors and simple digital and analog circuits (a NAND logic gate and a 1-bit ADC converter).
(Paper 4.6, “Large-Scale 2D Electronics Based on Single-Layer MoS2 Grown by Chemical Vapor Deposition,” H. Wang et al, M.I.T.)
SRAM replacement?
Researchers from Toshiba have attacked the problem SRAMs have with static power leakage as the devices shrink. They substituted perpendicular magnetic tunnel junctions (p-MTJs) for the SRAM cells normally used as CPU cache memory. Researchers successfully built a 30-nm p-MTJ having a 3-nanosecond write time and a low write current of 50 µA, resulting in only 0.09 pJ of programming energy required.
(Paper #29.4, “Impact of Ultra-Low Power and Fast Write Operation of Advanced Perpendicular MTJ on Power Reduction for High-Performance Mobile CPU,” E. Kitagawa et al, Toshiba)
Scaling highlights
Two of the more widely anticipated presentations come from two of the more widely known contributors to device innovation: Intel and IBM.
Intel will describe its 22-nm tri-Gate SoC technology, featuring high-speed logic transistors with subthreshold leakages ranging from 100 nA/µm to 1 nA/µm and low-power versions feature leakage of < 50 pA/µm. ( Paper #3.1, “A 22nm SoC Platform Technology Featuring 3-D Tri-Gate and High-k/Metal Gate, Optimized for Ultra-Low-Power, High-Performance and High-Density SoC Applications,” C.-H. Jan et al, Intel).
IBM will describe what it says is the world’s first high-performance hybrid-channel extremely thin SOI CMOS device, integrating a PFET having a thin, uniform strained SiGe channel, with an NFET having a Si channel, at 22nm geometries. An STI-last (isolation-last) process makes the hybrid architecture possible.
Click on image to enlarge.
(Paper #18.1, “High-Performance, Extremely Thin SOI (ETSOI) Hybrid CMOS with Si Channel NFET and Strained SiGe Channel PFET,” K. Cheng et al, IBM).
Related stories :
--IEDM targets next-gen memory technologies
--London Calling: At IEDM, heat improves flash memory
Graphene is the next big thing in device science and has been for many years now, the old joke goes. It's thin, carbon-based and offers high current density and electron mobility. IEDM will dedicate session 4 (Monday, 1:30 p.m. PST) to graphene and low-dimensional nano device technology.
But there may be a new sheriff in graphene town: Molybdenum Sulfide (MoS). Possessing some characteristics similar to graphene, MoS also claims a wide energy bandgap, enabling transistors and circuits to be built from it directly. An M.I.T.-led team will describe the use of CVD processing to grow uniform, flexible, single-molecular layers of MoS, comprising a layer of Mo atoms sandwiched between two layers of S atoms. They exploited the material’s 1.8 eV bandgap to build MoS transistors and simple digital and analog circuits (a NAND logic gate and a 1-bit ADC converter).
(Paper 4.6, “Large-Scale 2D Electronics Based on Single-Layer MoS2 Grown by Chemical Vapor Deposition,” H. Wang et al, M.I.T.)
Molybdenum sulfide (MoS) has similar characteristics but offers something graphene doesn’t: a wide energy bandgap, enabling transistors and circuits to be built from it directly.
SRAM replacement?
Researchers from Toshiba have attacked the problem SRAMs have with static power leakage as the devices shrink. They substituted perpendicular magnetic tunnel junctions (p-MTJs) for the SRAM cells normally used as CPU cache memory. Researchers successfully built a 30-nm p-MTJ having a 3-nanosecond write time and a low write current of 50 µA, resulting in only 0.09 pJ of programming energy required.
(Paper #29.4, “Impact of Ultra-Low Power and Fast Write Operation of Advanced Perpendicular MTJ on Power Reduction for High-Performance Mobile CPU,” E. Kitagawa et al, Toshiba)
Scaling highlights
Two of the more widely anticipated presentations come from two of the more widely known contributors to device innovation: Intel and IBM.
Intel will describe its 22-nm tri-Gate SoC technology, featuring high-speed logic transistors with subthreshold leakages ranging from 100 nA/µm to 1 nA/µm and low-power versions feature leakage of < 50 pA/µm. ( Paper #3.1, “A 22nm SoC Platform Technology Featuring 3-D Tri-Gate and High-k/Metal Gate, Optimized for Ultra-Low-Power, High-Performance and High-Density SoC Applications,” C.-H. Jan et al, Intel).
IBM will describe what it says is the world’s first high-performance hybrid-channel extremely thin SOI CMOS device, integrating a PFET having a thin, uniform strained SiGe channel, with an NFET having a Si channel, at 22nm geometries. An STI-last (isolation-last) process makes the hybrid architecture possible.
Click on image to enlarge.
The images above are of an electron microscope view at the top and an EDX (energy-dispersive X-ray) spectroscopic view below it of a SiGe-channel PFET with 6-nm channel thickness, 22-nm gate length, 100-nm contacted gate pitch, high-k/metal gate architecture and ISBD SiGe raised source drain.
(Paper #18.1, “High-Performance, Extremely Thin SOI (ETSOI) Hybrid CMOS with Si Channel NFET and Strained SiGe Channel PFET,” K. Cheng et al, IBM).
Related stories :
--IEDM targets next-gen memory technologies
--London Calling: At IEDM, heat improves flash memory
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kjdsfkjdshfkdshfvc
12/6/2012 10:54 AM EST
what , still no nano photonics devices in the pipeline, thats a shame,
if only someone made some Plasmonic Optical Tweezers Could Trap Tiny Proteins
An innovative aperture design based on plasmonics could focus light so effectively that tiny beams could trap and manipulate particles as small as a few atoms.
or we had a fiber optic spanner to adjust new Metamaterials and so Manipulate Light on a Microchip.
we probably need lots of sellotape ‘Smart’ Claw's
and OC the usual micron-scale spatial light modulator (SLM) that works in 3-D “free space” and runs orders of magnitude faster than those used in sensing and imaging devices today..
blah blah blah :)
did everyone at IEDM also forget Continuous gas-phase synthesis of nanowires with tunable properties
http://www.nature.com/nature/journal/vaop/ncurrent/full/nature11652.html
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song-chou-1
12/6/2012 11:07 AM EST
Intel's Finfet is best thing for foundry.
Intel keeps talking finFET but is not shipping 22nm FinFET products in mobile (feature-smart-phone or tablets) now or even next year.
After 2 years just 1 design is shipping(ivy bridge).
Achronix 22nm FPGA delayed until 2013
Haswell delayed to 2nd-half 2013
14nm delayed 1 year to 2nd-half 2014
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kjdsfkjdshfkdshfvc
12/6/2012 12:26 PM EST
actually does the "celeron" count in mobile sang-chou-1 ?
if so you will be finally seeing Celeron Ivy Bridge CPU's at the same time they release Haswell in the first half of 2013.
regarding that " tiny beams could trap and manipulate particles as small as a few atoms." rather than just light i always thought we don't use sound enough in electronics and heres just such a rather cool fully working project
using Ultra Tangibles
Creating movable tangible objects on interactive tables ultrasound is focussed into a beam, creating enough force to move lightweight objects across a surface.
mesmerizing video fukk of potential :)
http://big.cs.bris.ac.uk/projects/ultratangibles
scale this down to the micro/nano scale and it could be a very usable commercial product to manipulate particles and perhaps even perform some assembly, what you think , would nano scale ultrasound destroy the graphene nanowires etc http://www.graphene-info.com/electron-conductivity-studies-graphene-nanowires at the quantum mechanical process level
along side some Twisted beams of light could increase the capacity of optical communications.
http://www.nanomagazine.co.uk/index.php?option=com_content&view=article&id=1908:twisted-beams-of-light-could-increase-the-capacity-of-optical-communications-technology&catid=38:nano-news&Itemid=159
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