The next big thing?
Graphene is the next big thing in device science and has been for many
years now, the old joke goes.
It's thin, carbon-based and offers high current density and electron
mobility. IEDM will dedicate session 4 (Monday, 1:30 p.m. PST) to graphene and
low-dimensional nano device technology.
But there may be a new sheriff in graphene town: Molybdenum Sulfide
(MoS). Possessing some characteristics similar to graphene, MoS also
claims a wide energy bandgap, enabling transistors and circuits to
be built from it directly. An M.I.T.-led team will describe the use
of CVD processing to grow uniform, flexible, single-molecular layers
of MoS, comprising a layer of Mo atoms sandwiched between two layers
of S atoms. They exploited the material’s 1.8 eV bandgap to build
MoS transistors and simple digital and analog circuits (a NAND logic
gate and a 1-bit ADC converter).
(Paper 4.6, “Large-Scale 2D Electronics Based on Single-Layer
MoS2 Grown by Chemical Vapor Deposition,” H. Wang et al, M.I.T.)
Molybdenum sulfide (MoS) has similar characteristics but offers something graphene doesn’t: a wide energy bandgap, enabling transistors and circuits to be built from it directly.
Researchers from Toshiba have attacked the problem SRAMs have with
static power leakage as the devices shrink. They substituted
perpendicular magnetic tunnel junctions (p-MTJs) for the SRAM cells
normally used as CPU cache memory. Researchers successfully built a
30-nm p-MTJ having a 3-nanosecond write time and a low write current
of 50 µA, resulting in only 0.09 pJ of programming energy
(Paper #29.4, “Impact of Ultra-Low Power and Fast Write Operation
of Advanced Perpendicular MTJ on Power Reduction for
High-Performance Mobile CPU,” E. Kitagawa et al, Toshiba)
Two of the more widely anticipated presentations come from two of
the more widely known contributors to device innovation: Intel and
Intel will describe its 22-nm tri-Gate SoC technology, featuring
high-speed logic transistors with subthreshold leakages ranging from
100 nA/µm to 1 nA/µm and low-power versions feature
leakage of < 50 pA/µm. (
Paper #3.1, “A 22nm SoC Platform
Technology Featuring 3-D Tri-Gate and High-k/Metal Gate, Optimized
for Ultra-Low-Power, High-Performance and High-Density SoC
Applications,” C.-H. Jan et al, Intel).
IBM will describe what it says is the world’s first high-performance
hybrid-channel extremely thin SOI CMOS device, integrating a PFET
having a thin, uniform strained SiGe channel, with an NFET having a
Si channel, at 22nm geometries. An STI-last (isolation-last) process
makes the hybrid architecture possible.
Click on image to enlarge.
The images above are of an electron microscope view at the top and an EDX (energy-dispersive X-ray) spectroscopic view below it of a SiGe-channel PFET with 6-nm channel thickness, 22-nm gate length, 100-nm contacted gate pitch, high-k/metal gate architecture and ISBD SiGe raised source drain.
(Paper #18.1, “High-Performance, Extremely Thin SOI (ETSOI)
Hybrid CMOS with Si Channel NFET and Strained SiGe Channel PFET,”
K. Cheng et al, IBM).
targets next-gen memory technologies
Calling: At IEDM, heat improves flash memory