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resistion
At 10 nm, probably half of the layers are double patterning, the other half is ...
iniewski
20nm transistor costing more?! This should had sent shock waves thru this ...
Broadcom sees rising 20 nm costs amid handset push
Rick Merritt
12/6/2012 3:30 PM EST
SAN JOSE, Calif. – Cost-per-transistor may rise at the 20- and 14-nm generations, Broadcom CEO Scott McGregor said during in the company’s annual analyst day here. Nevertheless, the company will “judiciously” drive more products to newer nodes next year as it rolls out its first LTE chips and gears up for a push into integrated applications processors.
Separately, Broadcom expects handsets using its near-field communications chips will ramp next year. TVs and set-tops using 4K x 2K displays and the new high-efficiency video codec (likely to be re-named MPEG-5) will be a big focus at next month’s Consumer Electronics Show, he added.
“Moore’s Law is going through an interesting phase,” said McGregor. “We use to have improvement in cost per transistor at every node, and at 28 nm it’s coming down, but in 20 or 14 nm it may even come up and that may be a shock for everyone."
Nevertheless, Broadcom expects to gain economic advantages by driving a greater percentage of products to leading nodes when they need it for lower power or higher density.
“We have been a generation or two behind others in the node we use, but we believe it makes sense to move closer to the leading edge,” McGregor said. “We won’t be the first in a process tech but we will get more competitive."
“When we went to 65 nm, we moved the whole product portfolio, but that won’t happen going forward,” said McGregor. “We will be judicious, 28 nm will have long life and some products won’t make sense to move maybe ever and that is very different from the past."
Broadcom expects to tape out 50 new SoCs in 2012. “This is the engine of Broadcom’s growth, a large part of what you get for spending $2 billion in R&D,” according to McGregor.
Related stories:
Broadcom lifts Q4 sales target
Intel to detail tri-gate advances at IEDM
Qualcomm overtakes TI in chip sales rankings
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resistion
12/7/2012 1:11 AM EST
The margin per transistor may rise (compensating higher cost) if the power per transistor is lower. But even this scaling will be limited as well, by noise. 20 nm is already very small (anybody recall the electron mean free path?)
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song-chou-1
12/7/2012 7:42 AM EST
I attended and McGregor also said "20nm costing more will surprise market"
that is partly because Intel Marketing is talking different message
But I spoke to someone in Intel Procurement Group about why they are taping out LTE and RF mobile chips at TSMC 28nm. Intel guy said Intel's advanced internal nodes manufacturing (22 and 14nm) was not cost effective with foundry.
low cost mobile chips are going go stay at 28nm for industry and even Intel (using outside manufacturing)
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rick.merritt
12/7/2012 9:43 AM EST
Thanks Song Chou.
That strongly suggests Intel is not ready to supply foundry services to anything but cost insensitive parts such as FPGAs and router ASICs
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the_floating_ gate
12/7/2012 11:21 AM EST
Take a look at wafer price projections (past and future)
Nvidia deeply unhappy with TSMC, claims 20nm essentially worthless
http://www.extremetech.com/computing/123529-nvidia-deeply-unhappy-with-tsmc-claims-22nm-essentially-worthless
ASML stated just litho will be 1.7x for 20nm compared to 28nm
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rick.merritt
12/7/2012 11:54 AM EST
Of course, double patterning will raise costs even if all else was the same
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resistion
12/7/2012 12:03 PM EST
Well to be exact not every layer is double patterned. It's not automatic doubling of chip cost. It will be diluted by large number of non-doubled metal layers.
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the_floating_ gate
12/7/2012 3:43 PM EST
I thought Peter's article about Gloflo trying to break even in 2015 is pretty sobering.
It raises the question of how good are TSMC's 28nm margin during the first 12 months - TSMC has the advantage to make huge profits off legacy technology - Gloflo does not.
In the past Intel (and also AMD) used depreciated equipment to manufacture NOR flash -
perhaps 32nm Medfield is using similar approach being fabbed with more or less depreciated 45nm equipment.
Paul O. made also some comments about foundry bizz during Bernstein presentation -
no intention to compete with TSMC rather focusing on "value" deals without compromising the core business.
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the_floating_ gate
12/7/2012 10:32 PM EST
But I spoke to someone in Intel Procurement Group about why they are taping out LTE and RF mobile chips at TSMC 28nm. Intel guy said Intel's advanced internal nodes manufacturing (22 and 14nm) was not cost effective with foundry.
Maybe this has to do with opportunity cost
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BJ-5
12/7/2012 10:12 AM EST
Rick,
100% correct. Intel's manufacturing for foundry and internal products only is viable due to cost for it's $100-1000 CPU and select high margin FPGA and ASICs.
Someday the analysis will understand Intel does not have a manufacturing advantage for cost sensitive mobile or foundry to Apple.
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rick.merritt
12/7/2012 11:54 AM EST
What's the implication for Intel's own mobile SoCs aka Medfield and follow ons?
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BJ-5
12/7/2012 3:05 PM EST
Rick,
Implication for Intel's first 22nm Valley view (Atom SOC) will have somewhere in the neighborhood 30-40% higher cost than equal parts from Qualcomm (snapdragon) or nVidia (Tegra 4) fabricated parts in foundry 28LP or 28HPM
but bigger problem is TAM is moving to integrated apps and base band on single SOC.
Valley view not having on die integrated LTE base band makes it uninteresting to market
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song-chou-1
12/7/2012 3:33 PM EST
Rick,
I look at it like this.
You can chip 28nm SOC with integrated application/base band processor now
or you can ship same transistor density chips in Intel's 22nm SOC in 2014 but only application processor
It should be clear why Intel is loosing in mobile and CEO is out.
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the_floating_ gate
12/7/2012 10:21 PM EST
"Implication for Intel's first 22nm Valley view (Atom SOC) will have somewhere in the neighborhood 30-40% higher cost than equal parts from Qualcomm (snapdragon) or nVidia (Tegra 4) fabricated parts in foundry 28LP or 28HPM"
I am curious how you came up with this number 30 to 40%
What's Valley View die size?
BRCM just reiterated NVDA's dim projection that Moore's law is slowing down significantly for the foundries and TI probably exited the mobile business for the very same reason.
GloFlo breaking even in 2015?
Very impressive
Disclosure : heavily invested in arms - I mean arms supplied by KLAC, LRCX & NVLS (double patterning) and ASML
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BJ-5
12/8/2012 9:09 AM EST
To: the_floating_gate,
Cost numbers come from our competitive analysis group . Has a program that calculated cost from die size, wafer, test and packaging cost.
Valley view die sizes are still all under NDA. But we know there are two version 2 or 4 cores and parts and the parts use ivy brige 2C graphic unit (~30mm^2 silicon area). The Atom cores will be about .8X smaller in 22 vs 32nm. Thus die size are is range 60-80mm^2
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resistion
12/8/2012 9:48 AM EST
I've had my suspicions intel's 22 nm added trigate process steps won't be cheaper than foundry 28 nm either.
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resistion
12/8/2012 9:52 AM EST
The fin pitch is 60 nm which is sublithographic, so requires double patterning. It's just one layer, but look at the gate and isolation pitches they are around 90 nm, which is also what foundry 28 nm offers. It's hard to argue that for this particular comparison, Intel has a cheaper process. Maybe they got performance and yield (which is another major cost factor).
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any1
12/10/2012 10:48 AM EST
I think that IDMs like Intel and Samsung still have an edge over the foundries due to their better integrated process technologies. I don't know that being 30% more expensive for an applications processor is such a big deal for Intel in the grand scheme of things either as long as the performance (both speed and low power) is there. The foundries will catch up eventually but it will take several more years.
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iniewski
12/10/2012 12:18 PM EST
20nm transistor costing more?! This should had sent shock waves thru this industry...time to start packing and heading for the exit? ;-)
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resistion
12/11/2012 7:49 AM EST
At 10 nm, probably half of the layers are double patterning, the other half is single-patterned, and only the fin layer is quadruple patterned. So this is maybe 50% extra cost, but the density is improved maybe 4X, so the cost per transistor is still reduced, just not as much.
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