News & Analysis
Intel's 22-nm tri-gate SoC, how low can you leak?
Sylvie Barak
12/10/2012 4:30 PM EST
SAN FRANCISCO -- Intel will describe its 22-nm tri-gate (FinFET) SoC technology for mobile applications Monday (Dec. 10) at the International Electron Devices Meeting (IEDM) here.
The chip maker introduced a CPU version of its 22-nm offering in June, but Intel senior fellow Mark Bohr said in an interview that the recipe has been tweaked in order to scale down to a more mobile, ultra-low leakage version.
The change means Intel will now be able to boast product support from high performance servers down to cell phones on a tri-gate 22-nm process, with transistors covering a wide range of performance barriers.
Intel’s new SoC technology also includes high voltage I/O transistors, precision resistors, capacitors and inductors that were not included on the original CPU version of the chip.
The SoC’s will be ready for high volume manufacturing in 2013, Bohr said.
Intel had tended to focus heavily on performance, but is now looking to widen its transistor scope. On the performance side of the scale is the CPU version of Ivy Bridge, which also exhibits higher power leakage. On the lower end of the scale, however, Intel is seeking to offering a range of choices.
“There isn’t just one version of our SoC technology," Bohr said. "We [will] offer a rich menu of options to pick and choose from, both different transistor options and different interconnect options,” said Bohr.
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sranje
12/10/2012 4:58 PM EST
Thank you Sylvie very much !
It would be interesting to hear what will be the impact on IC packaging.... Any information on that? Thanks once again
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SylvieBarak
12/10/2012 5:52 PM EST
My pleasure. I don't have any information on how this will affect the packaging just yet, but I'll try to find out for you. Glad you enjoyed the article!
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iniewski
12/10/2012 6:40 PM EST
The slide shows leakage getting smaller as the feature size decreases...this can't be true!!!
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resistion
12/10/2012 10:39 PM EST
This looks like (at least) a dual gate oxide SoC, so it's definitely more expensive to make than single gate oxide logic. Triple gate oxide is not unheard of either. The gate layer in this case is therefore already triple patterned for non-lithographic, electrical reasons alone.
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danny1024
12/11/2012 6:15 PM EST
Everyone who plays/played the "Master of Orion" or the "Civilization" series of global/galactic strategy games knows that "raping the tech tree" is the key to victory. I can't see how that's any different for the semiconductor industry and the process technology tree.
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WiLess
12/11/2012 8:10 PM EST
TSMC has an infrastructure and process to enable IP houses to develop analog, memory and other process-specific IP. That way anyone who uses the new process can choose from many offering. That's my understanding why Intel's mobile offerings are so poor-featured compared ARM-based developed by Qualcomm, Samsung and Nvidia. Tri-gate process is a great improvement and the step in the right direction to enable mobile market, but I am not sure if this is sufficient alone. Even if Intel opens its fab to others today, it still has a lot to catch up with the way other fabs are supporting their customers. Thanks for the interesting article!
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