Intel's 22-nm tri-gate SoC, how low can you leak?

Why FinFet is good for analog design

Bohr said it was now abundantly clear that 22-nm tri-gate SoCs outperformed 32-nm planar devices by a margin of 20 to 65 percent, while covering four different orders of magnitude in current leakage.



Intel said its 22-nm tri-gate product also exhibits superior short channel control, with optimum sub-threshold slope and drain-induced barrier lowering (DIBL). The sub-threshold slope allows for low leakage but could also function well at low voltage, making them “much better than the very best planar devices," Bohr added.

Bohr said the low numbers for DIBL seen in testing were a measure of good performance in short channel control, with the new SoC pulling in DIBL numbers of 30 to 35mVs, while comparable products had DIBL’s closer to the 100mV range.



Bohr said that when Intel had first announced it would be using tri-gate devices, other companies had argued that FinFET transistors would not aid analog design. “Well, they’re wrong,” declared Bohr.

For analog designers, he asserted, an important transistor metric is trans-conductance by power out (GM x Rout). Bohr said that while this value had been steadily degrading over the past few generations, it had shot up again in 22-nm trigate SoCs, making it easier for analog circuit designers to use than Intel’s previous three generations of planar technology.



Bohr also touted the technology's advanced passive features, including precision resistors, MIM capacitors and high Q inductors.