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Or_Bach
resistion
He also mentioned immersion (193 nm not EUV) for 7 nm, though that did surprise ...
IEDM: Moore’s Law seen hitting big bump at 14 nm
Rick Merritt
12/11/2012 12:01 AM EST
Test driving EUV
Click on image to enlarge.
Next: Road ahead
Earlier this year,
an Intel executive said the company believes it could make chips
economically even down to 10-nm design rules without EUV, using quad
patterning. Intel is believed to generally have higher costs of
manufacturing than the rest of the industry, due to the relatively high
price for its processors.
Intel, Samsung and TSMC have separately invested billions of dollars this year in ASML which is making the EUV systems. EUV requires a more powerful light source now in development at Cymer, which ASML acquired this year.
With the existing weak light source, today’s EUV systems pattern less than 20 wafers an hour. Chip makers need systems that can pattern more than 100 wafers/hour, said Ronse.
Intel, Samsung and TSMC have separately invested billions of dollars this year in ASML which is making the EUV systems. EUV requires a more powerful light source now in development at Cymer, which ASML acquired this year.
With the existing weak light source, today’s EUV systems pattern less than 20 wafers an hour. Chip makers need systems that can pattern more than 100 wafers/hour, said Ronse.
Click on image to enlarge.
Next: Road ahead
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seaEE
12/11/2012 1:23 AM EST
Murphy is always two steps behind Moore.
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elPresidente
12/11/2012 1:38 AM EST
Moore's law has been predicted to hit a major bump in the road since 500nm.
IMEC's R&D funding levels are based on the level of panic that is instilled in the industry.
"According to experts", then exclusively citing Chicken Littles from the same outfit, is a journalism joke EE Times (not aimed at you Rick - this is UBM's broad spectrum destruction of what was EET and EDN).
If it were Intel or IBM freaking out with a slideshow pitch, or even having one of their people cited in addition to IMEC, we might be justified in taking this R&D panhandling nonsense seriously.
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rick.merritt
12/11/2012 10:19 AM EST
Indeed, Intel's Mark Bohr whom I met and talked with briefly later in the day remains bullish.
See http://www.eetimes.com/electronics-news/4403075/IBM--Intel-face-off-in-22-nm-process-at-IEDM
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resistion
12/11/2012 4:49 AM EST
Imec bought EUV tools quite aggressively to get the member interest. But members beginning to understand not worth it.
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resistion
12/11/2012 4:54 AM EST
Upper metal layers should never require EUV or double patterning, so cost increase is exaggerated, obviously by EUV supporters.
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sprite0022
12/11/2012 10:37 PM EST
stop argument, time to place your bet now.
life is full of gambling, ultrabook, android,
who knows what ll happen just jump...
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unknown multiplier
12/12/2012 9:55 AM EST
GlobalFoundries already gave up on EUV it seems:
http://semimd.com/blog/2012/12/11/globalfoundries-accelerates-10nm-process/
“10nm will be optical,” he said. “We have evidence that we can do 7nm with immersion.”
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resistion
12/12/2012 9:56 AM EST
Remember to heed the warning of node renaming.
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jeremybirch
12/14/2012 7:08 AM EST
surely EUV is optical just a shorter wavelength source?!
Perhaps they mean optical vs ebeam?
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resistion
12/14/2012 9:21 AM EST
He also mentioned immersion (193 nm not EUV) for 7 nm, though that did surprise me somewhat.
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green_is_now
12/12/2012 7:03 PM EST
once upon a time...UV lithography impossible...
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green_is_now
12/12/2012 7:09 PM EST
The facts are in process shrink below 1/10th of wavelength will require multiple patterning.
where increased cost of EUV equipment break even with double, triple patterning costs still being played out with rapid development in the EUV space.
If they would just hire me it could go much faster.
:)
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green_is_now
12/12/2012 7:36 PM EST
What is the performance/leakage penalty at a given feature size for a given available wavelength?
193nm?
13.5nm?
If EUV allows feature shrink without performance/leakage penalty compared to UV used now for comperable cost EUV wins hands down.
Chasing moores law min feature size only and not performance/leakage metrics is not a solution
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resistion
12/12/2012 7:54 PM EST
The problem for EUV is it has only one application space and that window is shrinking. In addition, the higher energy associated with its higher resolution wavelength produced some fundamental new effects, e.g., ionization, shot noise, etc., which will require more time to be grasped.
On the other hand, 193 nm is more familiar, and the temptation to merely increase patterning steps is there. Although such increases will be more complex and costly, a detailed calculation, factoring in number of layers, volume, performance, power, etc. is needed to determine the overall cost impact to the particular product. There won't be a unique "right" answer unfortunately.
But as you implied, leakage gets worse, and interconnect performance will also get worse. So a breakout from this trend is needed, soon.
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Or_Bach
12/14/2012 11:04 PM EST
Yes,
As we been saying - Monolithic 3D is finally practical, so lets start to scale up, as scale down is no longer easy and full of benefits.
And it looks that the first vendors to reach this conclusion are the NAND NV vendors, as had been presented across this IEDM.
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