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bruzzer2
Red Hog
IBM, Intel face off at 22 nm
Rick Merritt
12/10/2012 8:29 PM EST
IBM ready for 3-D at 22 nm
Finally, Intel created two new transistor designs specifically for the 22-nm SoC variant. One is focused on low power and the other on high voltage for mixed-signal and analog circuits (see chart above).
For its part, IBM described its 22-nm process using partially depleted silicon-on-insulator. IBM “has prototyped a number of server processors” in the node that achieve latency below 1.5 ns and 750 MHz random clock cycles, said IBM researcher S. Narasimha.
Narasimha declined to give specifics of what IBM might achieve with the 22-nm node. However he did say the goal was to provide 25 to 35 percent boosts of the previous node which delivered server processors running up to 5.5 GHz and others with up to 80 Mbytes embedded DRAM.
IBM created an SRAM cell that measures 0.026 mm2 using the process. It also power supplies at 1.2V across a 550 mm2 die area, he said.
The process provides up to 15 levels of metal. The lowest five levels use 80-nm features, similar to the Intel process, and the top two levels support through-silicon vias for 3-D stacks with memory chips.
IBM will deliver a separate paper Wednesday on its 3-D stacking work.
Click on image to enlarge.
Finally, Intel created two new transistor designs specifically for the 22-nm SoC variant. One is focused on low power and the other on high voltage for mixed-signal and analog circuits (see chart above).
For its part, IBM described its 22-nm process using partially depleted silicon-on-insulator. IBM “has prototyped a number of server processors” in the node that achieve latency below 1.5 ns and 750 MHz random clock cycles, said IBM researcher S. Narasimha.
Narasimha declined to give specifics of what IBM might achieve with the 22-nm node. However he did say the goal was to provide 25 to 35 percent boosts of the previous node which delivered server processors running up to 5.5 GHz and others with up to 80 Mbytes embedded DRAM.
IBM created an SRAM cell that measures 0.026 mm2 using the process. It also power supplies at 1.2V across a 550 mm2 die area, he said.
The process provides up to 15 levels of metal. The lowest five levels use 80-nm features, similar to the Intel process, and the top two levels support through-silicon vias for 3-D stacks with memory chips.
IBM will deliver a separate paper Wednesday on its 3-D stacking work.
Click on image to enlarge.
Intel showed two new transistors designed for its 22 nm SoC process.
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3D Guy
12/11/2012 11:32 AM EST
I think Mark Bohr's comments may be relevant to the super high volume CPUs Intel makes. They may not be applicable to the SOCs others make at TSMC and GloFo.
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bruzzer2
12/11/2012 12:24 PM EST
I agree with 3D guy for Intel standard merchant product. Where SOCs do present another question including for Intel.
For any standard product short run through five quarters of production requires a very volume high peak to see a marginal cost reduction for pulling down the full run average. Foundries may not be as product focused on the line. And how many see greater than 100 million unit runs?
On QUANTA for determining Intel marginal cost of production jury is still out on whether there actually is a cost reduction per millimeter square of dice area from Sandy Bridge to Ivy Bridge. Increased Ivy dice suggest there should be on Intel’s standard integration rule of no more than 10% increase in wafer cost per generation, although that rule has been broken many times in the past. Then the question arises whether or not there will actually be demand for that volume of Ivy supply? Also knowing Sandy oversupplied still floods the channels.
Ivy frequency distribution suggests Intel is fibbing on the ease of manufacturing trigate and this analysts suspects work overtime to make the sort above 2.4 GHz.
Finally having accelerated at 32 nanometer from a commercial industrial art into 22 nanometers applied science what are the real RISK development costs over production alone which this analyst suggests are high.
Intel annual financial won’t necessarily reveal the whole story where the books have been substantially cooked for a very long time. With a new generation of Haswell product in the mix, this analyst believes RISK production costs are more likely to rise than stay flat or decline.
Mike Bruzzone
Camp Marketing
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Red Hog
12/11/2012 2:52 PM EST
Hi Mike
How do you mean Intel is cooking the books? Are you suggesting their GM is higher than it appears? I remember reading an EET article saying their costs per wafer are three times as high as TSMC.
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bruzzer2
12/12/2012 2:14 AM EST
Search web for TSMC & Intel wafer output.
2011 TSMC states 12,970,000 300 millimeter wafers are 1.5 times more than Intel or 8,646,667.
Searched for Intel 3rd party estimate, time was passing, stated TSMC.
TSMC 2011 Gross Revenue 14,540,000,000 / 12,970,000 = $498.24
TSMC 2011 Net Revenue $5,100,000,000 / 12,970,000 = $175
Intel 2011 Gross Revenue $59,999,000,000 / 8,646,667 = $6,936
Intel 2011 Net Revenue $12,942,000,000 / 8,646,667 = $1,497
Intel Gross Revenue per Wafer is 14x TSMC
Intel Net Revenue per Wafer is 3x TSMC
But no this is not what I meant by Intel cooking the books.
Most blatant is misrepresentation that annual cooperative advertising expense is marketing cost 1993 to 2011 totaling $29,786,000,000. That marketing cost is actually a combination of IDM customer’s rebated fee accruals known as Intel Inside tied charge back metered price discrimination and sales rewards for loyalty.
In tied charge back form total sum is a kick through paid by PC IDMs taken as rebated fee accrual by Intel on sales price passed through by Intel to sales agents for channel stocks movement reporting. As marketing kick back to sales agents is cost at 5.15% of in system processor price stuck to PC end buyer as hidden charge in sales invoice.
Another irregularity for economists, financiers, investors, competitors, customers is calculating extended Intel story problems that are processor shipment leaks through Intel and press sources for determining revenues and margins quarters into future time.
This form of RICO known as collusion by model places Intel gross revenue higher than Intel stated, appears to over report data center revenue and under report PC client group revenue.
Alternatively QUANTA higher revenue difference can be sign of poor yield, unsold inventory, unreported revenues concealing unreported cost centers, to offset product priced less than cost, employee and stakeholder theft.
Mike Bruzzone
Camp Marketing
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