IBM ready for 3-D at 22 nm
Finally, Intel created two new transistor designs specifically for the 22-nm SoC variant. One is focused on low power and the other on high voltage for mixed-signal and analog circuits (see chart above).
For its part, IBM described its 22-nm process using partially depleted silicon-on-insulator. IBM “has prototyped a number of server processors” in the node that achieve latency below 1.5 ns and 750 MHz random clock cycles, said IBM researcher S. Narasimha.
Narasimha declined to give specifics of what IBM might achieve with the 22-nm node. However he did say the goal was to provide 25 to 35 percent boosts of the previous node which delivered server processors running up to 5.5 GHz and others with up to 80 Mbytes embedded DRAM.
IBM created an SRAM cell that measures 0.026 mm2
using the process. It also power supplies at 1.2V across a 550 mm2 die area, he said.
The process provides up to 15 levels of metal. The lowest five levels use 80-nm features, similar to the Intel process, and the top two levels support through-silicon vias for 3-D stacks with memory chips.
IBM will deliver a separate paper Wednesday on its 3-D stacking work.
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Intel showed two new transistors designed for its 22 nm SoC process.