SuVolta reports 65nm parameter results at IEDM

SAN FRANCISCO -- At IEDM today SuVolta presents the results of analog and digital logic circuits designed with the company’s PowerShrink CMOS platform implemented in Fujitsu Semiconductor’s 65 nm process technology.

“The DDC-based technology is expected to be commercially available in the first half of 2013 in a 55nm process offering,” said Haruyoshi Yagi, corporate senior executive vice president at Fujitsu Semiconductor Limited.

In a SuVolta-Fujitsu Semiconductor jointly-authored paper at the International Electron Devices Meeting IEDM the authors compare the same circuits fabricated in Fujitsu Semiconductor’s standard process and using the Deeply Depleted Channel technology. 

The results show DDC technology provides approximately 30 percent performance increase in digital circuits at matched power when using a supply voltage of near 1.2V. The authors also demonstrate a 47 percent power reduction at matched performance when running the DDC technology with a 0.9V V_DD.

Fujitsu Semiconductor is SuVolta’s first licensee of the DDC technology. Since the collaboration was announced in June 2011, the companies have worked together to bring up the DDC technology at the 65nm and 55nm nodes.

At the 2011 IEDM conference, the companies presented low-power operation of SRAM blocks down to 0.425V supply voltage. At this year’s IEDM conference, SuVolta presents silicon results that demonstrate DDC technology in both higher-speed operation or lower-power operation, depending on design requirements.

The SuVolta-Fujitsu jointly-authored paper is entitled “A Highly Integrated 65nm SoC Process with Enhanced Power/Performance of Digital and Analog Circuits.”

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