IBM paves way for wearable electronics, folding displays

97% yield

IBM said it used ETSOI for two reasons. First, its characteristics include an ultra-thin body (60 angstroms) that allows aggressive channel scaling below 30 nm, "and therefore a high level of packing density obtained," Shahrjerdi said. The second feature is the undoped channel, which diminishes variability. This allows aggressive voltage scaling on a chip, he added.

To improve the mechanical flexibility, researchers removed excess silicon below the buried oxide using an etch process, he added.

A second step to improve flexibility involves transferring the circuit to a plastic substrate, then removing the "relatively thick" polyimide tape and nickel layer. The polyimide comes off because it is attached with a thermal release adhesive; the nickel is removed by means of a chemical etch, he noted.

IBM reported slight degradation of the delay characteristics for the flexible sample compared to its measured delay characteristics before the layer transfer, an more so on pFETs (a degradation in performance of 30-40 percent) than nFETs.

To determine the source of degradation, IBM controlled spalling on another ETSOI wafer using the same processing steps. This time it was bonded rigidly to a silicon wafer instead of being mounting on a plastic substrate. IBM concluded that the pFET performance degradation was caused by probe rather than stress induced by the spalling process.

Shahrjerdi claimed 97 percent yield in the lab, and any problems they encountered were related to the nickel-sputtering tool, which affected that layer.

He also claimed the process is reproduceable, "By knowing he stressor level in the nickle layer, it gives you the depth for the spalling,"  Shahrjerdi said. Variability was plus or minus 1 micron.

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