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Rchandta1
Given low volume, 3D stacking using TSV makes perfect sense. Reduction in power ...
nano_meter
IBM has been filling B323A in East Fishkill N.Y. for years with tooling for ...
IBM details 3-D server chip stacks
Rick Merritt
12/12/2012 12:01 AM EST
SAN JOSE, Calif. – IBM will provide a deeper look into its work on 3-D chip stacks at the International Electron Devices Meeting (IEDM) here, detailing work on stacks of 45-nm server processors with memory and transceivers.
Big Blue has long been expected to be among the early users of 3-D stacking to pair its server CPUs with memories for performance and power advantages. It has been collaborating with Micron on the Hybrid Memory Cube, a memory stack for just such applications.
“As scaling saturates, and lithography sputters to a grinding halt, these orthogonal scaling techniques will assume even more importance and continue to keep Moore’s ‘law’ alive,” wrote Subraman S. Iyer, a senior IBM technologist in the IEDM paper to be presented Wednesday (Dec. 12).
The paper shows IBM’s road map extending from embedded DRAM to various 3-D stacks with and without interposers using face-to-face and back-to-back stacks. In a separate paper, IBM disclosed the top two layers of metal in its new 22-nm process are optimized for use with through silicon vias needed for 3-D stacks.
“Embedded DRAM, 3D stacking, interposers and wafer-to-wafer integration are intrinsic to this [IBM] roadmap,” Iyer’s paper said.
Click on image to enlarge.
IEDM goes deep on 3-D circuits
IBM, Intel face-off in 22 nm process at IEDM
Moore’s Law predicted to hit big bump at 14 nm
Next: 2 Terabits/s throughput
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iniewski
12/12/2012 10:59 AM EST
Did they discuss cooling challenges?
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chipmonk
12/12/2012 11:33 AM EST
For some time IBM has not invested in leading edge Fabs . So they have a reason to pursue TSV based 3D stacking, partitioning of functions ( SRAM, I/O etc. ). The thermal and stress issues of 3D stacking w/ TSVs are only beginning to be studied and both routing and performance would be affected by these factors.
Integration at the Package level w/o compromising performance too much requires fine - pitch thin film interconnects and soon drilling holes ( TSVs ) in live Si. This is by no means cheap. By not building Fabs of the latest node IBM saves on Capital but their unit cost goes up because of expensive packaging. But they make large and expensive systems so additional part costs get buried.
Companies that sell less than million units of high priced chips ( e,g. FPGA ) are next in line for integration at Package level.
This is not the case for Consumer systems where the massive volume enables at least the leaders to build the latest Fabs and integrate everything ( as in a SoC ) on a single small chip. As some of the leading Fabless companies who have recently dabbled in 3D stacking etc. have found out, cost would be a big deterrent.
So for them its back to the Intel single chip approach ( but built at offshore Foundries )
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nano_meter
12/12/2012 4:52 PM EST
IBM has been filling B323A in East Fishkill N.Y. for years with tooling for advanced nodes. It seems to have been their plan all along. They are running 22nm and 14nm development in pretty good volumes on the latest immersion tools. I don't understand the reference to " has not invested in a leading edge Fab" for quite some time , there is still room to expand in the current building, and as far as I know, they can support at least the next two nodes there.
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Rchandta1
12/14/2012 5:48 PM EST
Given low volume, 3D stacking using TSV makes perfect sense. Reduction in power consumption would be unparalleled. .. But what about thermal dissipation?
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