2 Terabits/s throughput
The paper shows IBM’s road map extending from embedded DRAM to various 3-D stacks with and without interposers using face-to-face (see diagram below) and back-to-back stacks. In a separate paper, IBM disclosed the top two layers of metal in its new 22-nm process are optimized for use with through silicon vias needed for 3-D stacks.
“Embedded DRAM, 3-D stacking, interposers and wafer-to-wafer integration are intrinsic to this [IBM] roadmap,” Iyer said..
In one example, a 45-nm SOI-based processor with eDRAM is stacked with two SiGe BiCMOS transceiver chips. “The bandwidth between chips exceeds 2 Tbits/s, far greater than achievable by either ceramic or organic interposers,” Iyer wrote.
“This interposer technology which can also include decoupling capacitors for mid frequency power supply noise reduction is a key feature of the next step of the evolution of the embedded memory roadmap,” he added.
IBM was quick to caution that “die-to-die 3-D integration is a tedious process and is limited in the ability to achieve dense inter-die connections…but multi GByte [memory] stacks can be integrated with the processor cache stack on a silicon interposer.”
Iyer said IBM is using so-called fat copper wires for TSVs. Although nthey have a four-fold difference with silicon in their thermal coefficient of expansion “control of Cu microstructure can minimize the deleterious effects of this large mismatch,” Iyer wrote.
“The stacking process is very sensitive to die warpage and the handling of thin die and controlling their warpage are key challenges,” he added.
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