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HS_SemiPro
IBM will likely go to FinFet at 14nm. But IBM doesn't need to compete in ...
HS_SemiPro
Was there any paper from TSMC at IEDM talking about their Roadmap or showing ...
Intel's FinFETs approach draws fire from rivals
Rick Merritt
12/13/2012 11:45 AM EST
Exotic alternatives
Stanford University professor Krishna Saraswat argued for germanium and III-V materials, citing a number of IEDM papers and other conferences showing advances. “Germanium is very beneficial because in the future we will need optical interconnects at least off chip and germanium makes very good sense for both transistors and optical interconnects."
Saraswat noted fabs cannot readily support the separate needs for silicon, germanium and III-V materials. “You will have to appoint a psychiatrist for each manufacturing engineer because they will be tearing their hair out over passivation."
Aaron Thean, a director of advanced devices at the IMEC research center in Belgium, argued for a more distant future that embraces tunnel FETs working in devices at near threshold voltage levels. However he was quick to admit they “are very painful devices to make work right.”
“The device community still needs to better understand the physics of these devices,” he said.
Hu of UC-Berkeley took a roughly similar position, calling for use of pillar tunneling transistors and designs that operate on fractions of a volt as a path to “true 3-D” chips. Tunneling transistors are “a building block that’s far away but we should be thinking about it,” he said.
Click on image to enlarge.
Next: 10-nm planar process
Stanford University professor Krishna Saraswat argued for germanium and III-V materials, citing a number of IEDM papers and other conferences showing advances. “Germanium is very beneficial because in the future we will need optical interconnects at least off chip and germanium makes very good sense for both transistors and optical interconnects."
Saraswat noted fabs cannot readily support the separate needs for silicon, germanium and III-V materials. “You will have to appoint a psychiatrist for each manufacturing engineer because they will be tearing their hair out over passivation."
Aaron Thean, a director of advanced devices at the IMEC research center in Belgium, argued for a more distant future that embraces tunnel FETs working in devices at near threshold voltage levels. However he was quick to admit they “are very painful devices to make work right.”
“The device community still needs to better understand the physics of these devices,” he said.
Hu of UC-Berkeley took a roughly similar position, calling for use of pillar tunneling transistors and designs that operate on fractions of a volt as a path to “true 3-D” chips. Tunneling transistors are “a building block that’s far away but we should be thinking about it,” he said.
Click on image to enlarge.
Next: 10-nm planar process
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rick.merritt
12/13/2012 2:52 PM EST
Are you backing FinFETs? FD-SOI? Gemanium? Tunnel FETs? and why?
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song-chou-1
12/13/2012 4:58 PM EST
Rick
3 big customers have committed to making foundry planar 20nm next volume node versus pick 20nm finFET (called "14 or 16nm")
Rest still deciding. There is no meaningful data anywhere on foundry Finfet so perhaps they have the same problem as Intel.
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the_floating_ gate
12/13/2012 9:07 PM EST
IBM's left hand does not seem to know what the right hand is doing - the foundry manufacturing landscape appears in complete disarry - poor UMC "sucker" - no wait UMC figured out long before IBM that SiLK though it looked great on paper could be manufactured...
UMC licenses IBM technology for 20-nm FinFETs
www.eetimes.com › News and Analysis
Jun 29, 2012 – (UMC) has licensed technology from IBM Corp. to expedite the development of its 20-nm CMOS process, including FinFET 3-D transistors, the ...
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the_floating_ gate
12/13/2012 9:08 PM EST
could NOT be manufactured
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giriscitek
12/13/2012 10:32 PM EST
I want to go with FD-SOI because when the substrate is fully depleted meaning no doping(theoretically) and hence the substrate will have very high resistance.
This means that the drain and source of MOS transistors can be very close as ST-Micro suggested less than 10nm (8 , 5 , ..) and still gate will have good control over the drain current which is crucial for MOS transitors to work properly.
FD-SOI will not be completely new step like Intel's 3D stacked MOS transistor architecture.
Hence FD-SOI will be more cost effective in terms of material cost of MOS transistor manufacture.
Digital MOS : FD-SOI , 3D or carbon wires will be good.
Analog MOS : ????? (for less than 10nm)
Carbon wires will be a boon for digital chips of the future with more than 10 billion switches on chip. may be good for memory as well like processor caches and SRAM kind.
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the_floating_ gate
12/13/2012 11:00 PM EST
Are you backing FinFETs? FD-SOI? Gemanium? Tunnel FETs? and why?
Why is AMD abandon SOI after using it for years?
AMD will therefore move on from SOI based processes next year. Kaveri that will replace Trinity will be made with 28 nanometer technology, which CTO (Chief Technology Office) Mark Papermaster confirms will be Bulk-based. The same year the cheap and energy efficient platforms Kabini and Temash will arrive, which will build on a similar 28 nanometer technology. There were not details on who will supply the process, but most likely Kaveri will be made by GlobalFoundries, while TSMC will produce Temash and Kabini.
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HS_SemiPro
12/14/2012 1:46 AM EST
Was there any paper from TSMC at IEDM talking about their Roadmap or showing that they have made progress with FinFet?
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HS_SemiPro
12/14/2012 1:50 AM EST
IBM will likely go to FinFet at 14nm. But IBM doesn't need to compete in Consumer Electronics market, their technology is optimized for Enterprise High Performance Servers,
SO they can afford SOI
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