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MClayton
Sounds like high stakes liar's poker...like when Toshiba gave many papers on ...
pinhead
Gate first and gate last drive some very different ground rules. So never ...
Foundries not dead, just evolving, says Globalfoundries CEO
Sylvie Barak
12/13/2012 5:02 PM EST
Moving to Foundry 2.0
“Like all living organisms, especially those in electronics, we have to continue to evolve,” he said, adding that its time to migrate to a new model he "Foundry 2.0."
“History has shown that closed systems rarely work,” said Manocha, calling for improved collaboration that would provide a “virtual IDM-like interface” to chip design companies to help close the gap between process teams at manufacturing companies and design teams at fabless firms.
Collaboration remains the only practical approach, Manocha argued, for meeting technical challenges like 3-D stacking, 450-mm fabs, multi-patterning and the long-term viability of extreme ultraviolet (EUV) lithography.
In order to survive and thrive, foundries must move away from single sources of supply, become more flexible, more transparent and less focused on optimizing individual products.
Among the the “big four” challenges faced by Globalfoundries faced over the next three years are: packaging, the transition to 450-mm, the cost of lithography/EUV and moving to new device architectures, including super-steep retrograde wells, fully-depleted silicon-on-insulator (FDSOI) and FinFETs.
To address customer needs, Manocha said Globalfoundries would have to cycle through three nodes in three years, introducing FinFETs at 14 nm.
“It’s not easy,” Manocha said, referring to the promise of delivering on a new node every year, but Globalfoundries is trying to think like it’s customers. “If customers want 10 nm by next year, we’ll be there."
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“Like all living organisms, especially those in electronics, we have to continue to evolve,” he said, adding that its time to migrate to a new model he "Foundry 2.0."
“History has shown that closed systems rarely work,” said Manocha, calling for improved collaboration that would provide a “virtual IDM-like interface” to chip design companies to help close the gap between process teams at manufacturing companies and design teams at fabless firms.
Collaboration remains the only practical approach, Manocha argued, for meeting technical challenges like 3-D stacking, 450-mm fabs, multi-patterning and the long-term viability of extreme ultraviolet (EUV) lithography.
In order to survive and thrive, foundries must move away from single sources of supply, become more flexible, more transparent and less focused on optimizing individual products.
Among the the “big four” challenges faced by Globalfoundries faced over the next three years are: packaging, the transition to 450-mm, the cost of lithography/EUV and moving to new device architectures, including super-steep retrograde wells, fully-depleted silicon-on-insulator (FDSOI) and FinFETs.
To address customer needs, Manocha said Globalfoundries would have to cycle through three nodes in three years, introducing FinFETs at 14 nm.
“It’s not easy,” Manocha said, referring to the promise of delivering on a new node every year, but Globalfoundries is trying to think like it’s customers. “If customers want 10 nm by next year, we’ll be there."
Related Stories
GlobalFoundries puts rivals on notice, tips 20-nm process
Globalfoundries appoints interim CEO
Globalfoundries looks to leapfrog fab rivals
GlobalFoundries charts road to 14 nm
Globalfoundries CEO says company is back on track
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giriscitek
12/13/2012 10:37 PM EST
Foundries need lot of money to go forward especially from 2014 because of high cost of manufacturing equipment and increased cost of living !
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the_floating_ gate
12/13/2012 10:48 PM EST
“If customers want 10-nm by next year, we’ll be there,” he concluded.
I admit I only glanced at it but this caught my eye - is he serious?
Morris Chang was talking about building a dedicated fab for large customer(s) - to me this approach is closer to the IDM model rather the foundry model.
The real economic challenge the way I see it is tremendous amount of fix cost that require very, very large unit volume ramping up quickly.
ASML made some interesting comments in regards to litho IDM process versus foundry process.
Due to design rules/shrink factor foundries would not be able to use multi patterning @14nm -
they would need EUV and it's doubtful EUV will be production worthy by that time while Intel can fall back on multi patterning
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SylvieBarak
12/14/2012 12:00 PM EST
He repeated it more than once. He also said it to press at the after session Q&A....
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resistion
12/14/2012 1:14 AM EST
I think the cost of making sub-lithographic pitch fins in FinFETs got glossed over. It would introduce double patterning even at today's 28 nm node.
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Austin Tech Watcher
12/14/2012 9:02 AM EST
IBM is not on the list of companies moving past 28nm, which revives the idea that IBM and GF will essentially merge. Or did he just forget to put them on the list?
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pinhead
12/14/2012 12:36 PM EST
I think IBM has a pretty meaningless share of the advanced node foundry business. They do develop and manufacture the technologies, but most of their capacity is for internal consumption. I assumed that this is why he left them out of his list.
I think his list is self serving anyhow. SMIC and UMC are probably both going to play in the advanced node space sooner or later (heck, UMC is probably already there).
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nano_meter
12/14/2012 4:54 PM EST
IBM would have to think long and hard before giving up control of wafer manufacturing and seeding it to a foundry like GF. The decision point for them is obviously what happens when 450 mm is required. Do they make that huge investment in another FAB ? Everyone down plays the importance of hardware in their product mix, but a great deal of their profit is generated, by, and around, system Z a unique microprocessor. Do they want to become just another foundry customer and tie their destiny to another company?
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the_floating_ gate
12/14/2012 6:38 PM EST
Solid State technology just reported that IBM presented a paper on advanced 22nm processing and they are using gate first - I repeat gate first!
I am baffled.
http://www.electroiq.com/blogs/chipworks_real_chips_blog/2012/12/ibm-surprises-with-22nm-details-at-iedm.html
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pinhead
12/17/2012 1:20 PM EST
Gate first and gate last drive some very different ground rules. So never underestimate the power of a designer to influence ground rules if he or she is intent on scaling their design from one node to the next rather than redesigning.
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MClayton
12/17/2012 4:55 PM EST
Sounds like high stakes liar's poker...like when Toshiba gave many papers on trench DRAM for next node at that time, and then stuck to planar and grabbed the market while competitors were attempting trench...one node too soon. (At least that is how I remember it long ago). R/D papers vs real fast ramp manufacturing leads to dangerous guessing. Colonel Boyd's disruptive jet dog fights in Korean war beat back the faster MIG's and saved US pilots and planes, using random "early moves" to tire the enemy, costing them the battles. Strike when the enemy is tired...or broke.
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