News & Analysis
Blue Pearl Software opens Japan office
Clive Maxfield
12/19/2012 5:29 PM EST
The folks at Blue Pearl Software, a provider of EDA software that accelerates RTL signoff for FPGA designs, have opened a Japan office in Tokyo, and appointed Katsuhiko Sakano as its Director of Sales.
“By opening this office and adding an experienced executive like Sakano to our management team, we continue to support our growing list of Japanese FPGA designers,” said Ellis Smith, Blue Pearl’s CEO.
“We are dedicated to providing FPGA designers in Japan with the best design tools for their innovative embedded systems and quality electronic products,” noted Sakano. “The Blue Pearl Software Suite runs on Windows, is easy to use, and is priced right. It also accelerates RTL signoff, supports SystemVerilog, and works with FPGA design flows supported by Xilinx and Synopsys.”
Sakano is an experienced EDA sales executive, who previously worked with Real Intent, Inc. and Springsoft K. K. (now part of Synopsys, Inc.), as well as Cadence Design Systems and leading semiconductor and FPGA companies.
Japan Contact Information for Blue Pearl Software
About the Blue Pearl Software Suite for FPGA RTL Signoff
The Blue Pearl Software Suite works with the Xilinx Vivado Design Suite running on Windows platforms. It includes linting, CDC analysis and automatic SDC generation. Its generated SDCs drive the efficiency of the synthesis and place and route phases of FPGA design implementation, and reduce iterations and overall design time. Its Visual Verification Environment makes it easy to use.
The company’s collaboration with Synopsys offers an optimized flow that works with Synopsys’ Synplify Pro FPGA synthesis software. Verilog, VHDL and SystemVerilog designers can automatically generate an exhaustive set of constraints that address false and multi-cycle paths that are compatible with Synopsys’ synthesis flow.
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
“By opening this office and adding an experienced executive like Sakano to our management team, we continue to support our growing list of Japanese FPGA designers,” said Ellis Smith, Blue Pearl’s CEO.
“We are dedicated to providing FPGA designers in Japan with the best design tools for their innovative embedded systems and quality electronic products,” noted Sakano. “The Blue Pearl Software Suite runs on Windows, is easy to use, and is priced right. It also accelerates RTL signoff, supports SystemVerilog, and works with FPGA design flows supported by Xilinx and Synopsys.”
Sakano is an experienced EDA sales executive, who previously worked with Real Intent, Inc. and Springsoft K. K. (now part of Synopsys, Inc.), as well as Cadence Design Systems and leading semiconductor and FPGA companies.
Japan Contact Information for Blue Pearl Software
Blue Pearl Software
Shinjuku Nomura Building, Tokyo
Level 32, Shinjuku Nomura Building
1-26-2 Nishi-Shinjuku, Shinjuku-ku
Tokyo, Japan 163-0532
Tel: +81 3 5322 2856
Ksakano@bluepearlsoftware.com
About the Blue Pearl Software Suite for FPGA RTL Signoff
The Blue Pearl Software Suite works with the Xilinx Vivado Design Suite running on Windows platforms. It includes linting, CDC analysis and automatic SDC generation. Its generated SDCs drive the efficiency of the synthesis and place and route phases of FPGA design implementation, and reduce iterations and overall design time. Its Visual Verification Environment makes it easy to use.
The company’s collaboration with Synopsys offers an optimized flow that works with Synopsys’ Synplify Pro FPGA synthesis software. Verilog, VHDL and SystemVerilog designers can automatically generate an exhaustive set of constraints that address false and multi-cycle paths that are compatible with Synopsys’ synthesis flow.
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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