News & Analysis
DesignCon's 5 Toughest Tech Questions
Rick Merritt
12/28/2012 12:40 PM EST
What are the issues for 3-D interconnects?
An interface is an interface—even when it is a tiny copper filament bored through one chip and into another. So no surprise a handful of DesignCon sessions will look at signaling issues for the through silicon vias used in various kinds of 3-D chip stacks.
Rambus will talk about its work with 2.5-D silicon interposers, and Korea’s Advanced Institute of Science and Technology will deliver two papers on 3-D chip stacks—one on its work on 2.5-D designs that lay a graphics chip and memory side-by-side on a substrate.
Interestingly, a top engineering manager from Nvidia is one of the keynoters. I speculated recently it is working on just such chips with Apple, although many have pooh-poohed my guesswork.
Rambus will talk about its work with 2.5-D silicon interposers, and Korea’s Advanced Institute of Science and Technology will deliver two papers on 3-D chip stacks—one on its work on 2.5-D designs that lay a graphics chip and memory side-by-side on a substrate.
Interestingly, a top engineering manager from Nvidia is one of the keynoters. I speculated recently it is working on just such chips with Apple, although many have pooh-poohed my guesswork.
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rick.merritt
12/29/2012 4:43 PM EST
What are your burning questions in high-speed design? Join the conversation.
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docdivakar
1/1/2013 5:12 PM EST
Rick, I am looking forward to your next five... I would be curious to know what KAIST is going to present on 3D Stacks (haven't seen much from them on this).
Regarding 400Gbits systems, it could herald the beginning of the end of Copper chassis-to-chassis interconnects as we know it; for sure it will restrict the application to within cabinet interconnects. But there are still challenges on motherboards -need better dielectric materials which will drive up the costs, not to mention power and signal routing and signal integrity.
MP Divakar
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rick.merritt
1/2/2013 4:40 PM EST
KAIST has two 3-D papers at the event. One on TSV failures and the other looks more interesting on 2.5-D GPU and memory.
See http://www.designcon.com/santaclara/conference/tracks.php?session_id=239
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docdivakar
1/3/2013 12:34 PM EST
Rick, thanks for the link. I am caught up with emails from the holiday break and found the work of Prof. Joungho Kim of KAIST in Phil Garou's article:
http://www.electroiq.com/blogs/insights_from_leading_edge/2012/12/iftle-126-2012-gatech-interposer-conference-part-2.html?cmpid=EnlAPDecember192012
The link above describes some work of KAIST on glass interposers vs. Silicon. Interesting thing is that it is also the first instance where I see optical wave guides in the context of 2.5D/3D stacking.
MP Divakar
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martin.rowe
1/2/2013 11:14 AM EST
Be sure to vote on "Are You Attending DesignCon 2013?" at DesignConCommunity.com.
We're always looking for new bloggers at DesignCon Community. If interested, send e-mail to
editors@designconcommunity.com.
See you in Santa Clara.
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nannasin28
1/21/2013 3:28 AM EST
there are still challenges on motherboards -need better dielectric materials. http://www.hqew.net
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