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Yang Zhiwei
Anything else to say, expect it!
docdivakar
Rick: the solution for handling losses caused by the woven glass PCB's is one ...
DesignCon SMEs: Tough Path to 25G+ High-Speed Signals
Rick Merritt
1/11/2013 10:00 AM EST
To 40G and beyond
“Electrical signaling is not necessarily dead after 25G,” says Adam Healey, a systems architect at LSI Corp., referring to one of three papers he co-authored for DesignCon 2013.
The paper reports on a simulation Healey helped conduct showing 40G and even faster interfaces may be viable given existing and advanced serdes and signal integrity techniques. “If you assume reasonable silicon scaling, you can get healthy looking eyes at these higher speeds,” said Healey, another veteran of the event.
That opens the door for cost- and space-reduced versions of today’s four-lane, 40G Ethernet products collapsed into a single lane. It also points the way to new interfaces such as 64G Fibre Channel even though the 32G version is still being hammered out.
The faster speeds will require more sophisticated modulation techniques such as four-level pulse amplitude modulation. The hyper-efficient PAM-4 is already being written into the draft 100GBaseKP4 standard for running 100G signals over today’s 10G backplanes, Healey said.
No one has implemented such sophisticated signaling yet, Healey said, but it’s coming. “At 10G, people didn’t need it; at 25G some people want it; and going to 40G and beyond…” you may have to give it a spin despite the trade-off of lower immunity to noise, he said.
Meanwhile, a gradual transition is clearly ahead. Engineers working on brand new designs that they want to last for awhile might consider this a good time to explore use of optical channels
“A lot of technologies being considered for on-chip and chip-to-chip optics are relatively new with unknown cost and risk factors, but they deliver a clear path for bandwidth scalability,” Healey said. “Each OEM will have to make some tough decisions on a case-by-case basis about what they use,” he added.
DesignCon 2013 papers co-authored by Adam Healey:
Beyond 25G
Equalization in high-speed serial systems
Statistical analysis of serdes
Next: The secret life of vias
“Electrical signaling is not necessarily dead after 25G,” says Adam Healey, a systems architect at LSI Corp., referring to one of three papers he co-authored for DesignCon 2013.
The paper reports on a simulation Healey helped conduct showing 40G and even faster interfaces may be viable given existing and advanced serdes and signal integrity techniques. “If you assume reasonable silicon scaling, you can get healthy looking eyes at these higher speeds,” said Healey, another veteran of the event.
That opens the door for cost- and space-reduced versions of today’s four-lane, 40G Ethernet products collapsed into a single lane. It also points the way to new interfaces such as 64G Fibre Channel even though the 32G version is still being hammered out.
The faster speeds will require more sophisticated modulation techniques such as four-level pulse amplitude modulation. The hyper-efficient PAM-4 is already being written into the draft 100GBaseKP4 standard for running 100G signals over today’s 10G backplanes, Healey said.
No one has implemented such sophisticated signaling yet, Healey said, but it’s coming. “At 10G, people didn’t need it; at 25G some people want it; and going to 40G and beyond…” you may have to give it a spin despite the trade-off of lower immunity to noise, he said.
Meanwhile, a gradual transition is clearly ahead. Engineers working on brand new designs that they want to last for awhile might consider this a good time to explore use of optical channels
“A lot of technologies being considered for on-chip and chip-to-chip optics are relatively new with unknown cost and risk factors, but they deliver a clear path for bandwidth scalability,” Healey said. “Each OEM will have to make some tough decisions on a case-by-case basis about what they use,” he added.
DesignCon 2013 papers co-authored by Adam Healey:
Beyond 25G
Equalization in high-speed serial systems
Statistical analysis of serdes
Next: The secret life of vias
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iniewski
1/11/2013 12:21 PM EST
What kind of clock recovery architecture is used at 25 Gb/s?
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rick.merritt
1/11/2013 12:22 PM EST
What bugaboos are you wrestling with at 25G?
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docdivakar
1/21/2013 1:46 PM EST
Rick: the solution for handling losses caused by the woven glass PCB's is one part of the solution -I would imagine it ensures a more uniform dielectric field alleviating the need for more expensive dielectrics. The other that is mentioned hits home to me -package is going to be a big issue. In addition to routing challenges for the exploding number of connections, minimizing reflections at the package-to-board interface is indeed a problem at higher signaling rates.
MP Divakar
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EDWARDP.SAYRE
1/11/2013 2:59 PM EST
NESA has worked on high speed serial problems for a long time (see EE Times, 8/17/1998). Some of the major problems for the IEEE 25/100 Gbps 802.3bj committee are the important design concepts to specify and how they relate to the IEEE 10/40 Gbps 802.3ae technology. From a physical designers point of view, a major problem is where and how to find and accumulate the technical application notes and form a coherent end to end reliable design. Few tools are appropriate for this level of design. A deep appreciation of advanced fundamentals as they relate to PCB materials, microwave and digital interconnect theory and design are required. Consultants such as myself and Scott McMorrow can fill the gap where there isn't a large and experienced SI staff.
Sincerely,
Ed Sayre, CTO
North East Systems Associates, Inc. (NESA)
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Yang Zhiwei
1/22/2013 10:53 PM EST
Anything else to say, expect it!
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