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Yang Zhiwei
Anything else to say, expect it!
docdivakar
Rick: the solution for handling losses caused by the woven glass PCB's is one ...
DesignCon SMEs: Tough Path to 25G+ High-Speed Signals
Rick Merritt
1/11/2013 10:00 AM EST
The secret life of vias
Like many high-speed design experts, Donald Telian is exploring the small, hidden places where problems hide. His DesignCon 2013 paper talks about losses in vias and via models.
“Most people have been staring at channels and long runs but with back drilling, vias have been problematic for a long time,” said Telian a signal integrity consultant for SI Guys (Oakhurst, Calif.). “It may be less than a tenth of a percent of the channel length, but it’s an important area,” he said.
Looking at the big picture, this DesignCon is really all about figuring out how to make the shift from 10 to 25G products, said Telian, echoing McMorrow and others. That involves work both in the passive channel and the silicon, said Telian who designed signal integrity for the original PCI bus.
Some of the new pc board materials hold promise of cutting losses nearly ten-fold, he said. As for the chips, “gates are still essentially free, and that’s turning into some really good equalization,” he added.
Engineers are moving to techniques such as three taps of decision feedback equalization to capture signals. “We started in the transmitter, now we’ve jumped to the receiver and that takes more intelligence because you are flying blind, but that’s where the action is today,” he said.
DesignCon resources:
Donald Telian’s paper on vias
Like many high-speed design experts, Donald Telian is exploring the small, hidden places where problems hide. His DesignCon 2013 paper talks about losses in vias and via models.
“Most people have been staring at channels and long runs but with back drilling, vias have been problematic for a long time,” said Telian a signal integrity consultant for SI Guys (Oakhurst, Calif.). “It may be less than a tenth of a percent of the channel length, but it’s an important area,” he said.
Looking at the big picture, this DesignCon is really all about figuring out how to make the shift from 10 to 25G products, said Telian, echoing McMorrow and others. That involves work both in the passive channel and the silicon, said Telian who designed signal integrity for the original PCI bus.
Some of the new pc board materials hold promise of cutting losses nearly ten-fold, he said. As for the chips, “gates are still essentially free, and that’s turning into some really good equalization,” he added.
Engineers are moving to techniques such as three taps of decision feedback equalization to capture signals. “We started in the transmitter, now we’ve jumped to the receiver and that takes more intelligence because you are flying blind, but that’s where the action is today,” he said.
DesignCon resources:
Donald Telian’s paper on vias
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iniewski
1/11/2013 12:21 PM EST
What kind of clock recovery architecture is used at 25 Gb/s?
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rick.merritt
1/11/2013 12:22 PM EST
What bugaboos are you wrestling with at 25G?
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docdivakar
1/21/2013 1:46 PM EST
Rick: the solution for handling losses caused by the woven glass PCB's is one part of the solution -I would imagine it ensures a more uniform dielectric field alleviating the need for more expensive dielectrics. The other that is mentioned hits home to me -package is going to be a big issue. In addition to routing challenges for the exploding number of connections, minimizing reflections at the package-to-board interface is indeed a problem at higher signaling rates.
MP Divakar
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EDWARDP.SAYRE
1/11/2013 2:59 PM EST
NESA has worked on high speed serial problems for a long time (see EE Times, 8/17/1998). Some of the major problems for the IEEE 25/100 Gbps 802.3bj committee are the important design concepts to specify and how they relate to the IEEE 10/40 Gbps 802.3ae technology. From a physical designers point of view, a major problem is where and how to find and accumulate the technical application notes and form a coherent end to end reliable design. Few tools are appropriate for this level of design. A deep appreciation of advanced fundamentals as they relate to PCB materials, microwave and digital interconnect theory and design are required. Consultants such as myself and Scott McMorrow can fill the gap where there isn't a large and experienced SI staff.
Sincerely,
Ed Sayre, CTO
North East Systems Associates, Inc. (NESA)
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Yang Zhiwei
1/22/2013 10:53 PM EST
Anything else to say, expect it!
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