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Yang Zhiwei
Anything else to say, expect it!
docdivakar
Rick: the solution for handling losses caused by the woven glass PCB's is one ...
DesignCon SMEs: Tough Path to 25G+ High-Speed Signals
Rick Merritt
1/11/2013 10:00 AM EST
Oracle poses two questions
Istvan Novak, a distinguished engineer helping build big iron servers at Oracle, brings at least two specific questions to DesignCon this year.
When using a time-domain reflectometer to measure impedance on today’s high-density boards the system “appears to be artificially out of spec for a number of cases,” Novak said. “This year there are significant limitations because we are pushing longer traces with higher density boards, so there’s more resistance,” he explained.
It’s no small issue, given impedance is the main metric for validating an electrical spec. “So what I am looking for is feedback from OEMs, pcb makers, maybe even some academics on solutions for this problem,” he said.
Novak also has been dogged by problems using the miniature differential probes on vector network analyzers to test an interconnect. “There are open exposed metal pieces of the contact which will have coupling between them, and currently none of the commercial calibration processes take out those interactions so we end up doing a measurement with a kind of systematic error--how do we correct for that?” he asked.
As a veteran member of the DesignCon tech advisory board, he has already had a chance to review several papers similar to those from Ritchey, Healey and Telian.
“Over the years this event has become for us the compass showing the direction to go,” he said. “If you just go and listen to what people talk about, you get a pretty good cross section of what the industry needs to address,” he said.
[Click here to register for DesignCon 2013, Jan. 28-31 at the Santa Clara Convention Center. Options range from an All-Access Pass to Free Expo Admission, which includes the option to attend a dozen tech training sessions.].
DesignCon resources:
Track on test and measurement methods
Keynote by National Instruments’ business and technology fellow
Istvan Novak, a distinguished engineer helping build big iron servers at Oracle, brings at least two specific questions to DesignCon this year.
When using a time-domain reflectometer to measure impedance on today’s high-density boards the system “appears to be artificially out of spec for a number of cases,” Novak said. “This year there are significant limitations because we are pushing longer traces with higher density boards, so there’s more resistance,” he explained.
It’s no small issue, given impedance is the main metric for validating an electrical spec. “So what I am looking for is feedback from OEMs, pcb makers, maybe even some academics on solutions for this problem,” he said.
Novak also has been dogged by problems using the miniature differential probes on vector network analyzers to test an interconnect. “There are open exposed metal pieces of the contact which will have coupling between them, and currently none of the commercial calibration processes take out those interactions so we end up doing a measurement with a kind of systematic error--how do we correct for that?” he asked.
As a veteran member of the DesignCon tech advisory board, he has already had a chance to review several papers similar to those from Ritchey, Healey and Telian.
“Over the years this event has become for us the compass showing the direction to go,” he said. “If you just go and listen to what people talk about, you get a pretty good cross section of what the industry needs to address,” he said.
[Click here to register for DesignCon 2013, Jan. 28-31 at the Santa Clara Convention Center. Options range from an All-Access Pass to Free Expo Admission, which includes the option to attend a dozen tech training sessions.].
DesignCon resources:
Track on test and measurement methods
Keynote by National Instruments’ business and technology fellow
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iniewski
1/11/2013 12:21 PM EST
What kind of clock recovery architecture is used at 25 Gb/s?
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rick.merritt
1/11/2013 12:22 PM EST
What bugaboos are you wrestling with at 25G?
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docdivakar
1/21/2013 1:46 PM EST
Rick: the solution for handling losses caused by the woven glass PCB's is one part of the solution -I would imagine it ensures a more uniform dielectric field alleviating the need for more expensive dielectrics. The other that is mentioned hits home to me -package is going to be a big issue. In addition to routing challenges for the exploding number of connections, minimizing reflections at the package-to-board interface is indeed a problem at higher signaling rates.
MP Divakar
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EDWARDP.SAYRE
1/11/2013 2:59 PM EST
NESA has worked on high speed serial problems for a long time (see EE Times, 8/17/1998). Some of the major problems for the IEEE 25/100 Gbps 802.3bj committee are the important design concepts to specify and how they relate to the IEEE 10/40 Gbps 802.3ae technology. From a physical designers point of view, a major problem is where and how to find and accumulate the technical application notes and form a coherent end to end reliable design. Few tools are appropriate for this level of design. A deep appreciation of advanced fundamentals as they relate to PCB materials, microwave and digital interconnect theory and design are required. Consultants such as myself and Scott McMorrow can fill the gap where there isn't a large and experienced SI staff.
Sincerely,
Ed Sayre, CTO
North East Systems Associates, Inc. (NESA)
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Yang Zhiwei
1/22/2013 10:53 PM EST
Anything else to say, expect it!
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