In the early days of digital electronics a good architectural idea could be implemented and the advantage it granted could be expected to apply for all foreseeable manufacturing generations. But now the complexity and pace of change of chip manufacturing is such that ideas and techniques sometimes struggle to last without significant re-invention.
"Big-little" is the idea, from processor licensor ARM Holdings plc (Cambridge, England), of pairing a performance-optimized processor core with a low-power standby-optimized processor core. It enables application software to switch between the cores for an overall energy saving in typical use where equipment spends much of its time in standby mode. ARM has prepared two processors cores, the Cortex-A15 and the Cortex-A7, to help implement the strategy and the idea is starting to come through in commercial products. Two examples are the Exynos 5 Octa
applications processor from Samsung and the MP6530
from Renesas Mobile.
But can big-little last and, if not, how must it be re-invented?
For a start we must consider that big-little is itself a reinvention of, or complement to, dynamic voltage and frequency scaling (DVFS).
DVFS is the idea that you can wind the voltage and clock frequency down on a given core to save dynamic power consumption at low performance and then wind them up to achieve a necessary application performance level. So an application starts on the Cortex-A7 it goes up through the DVFS "gears" until it is at top voltage and clock frequency and then jumps across to the Cortex-A15 where it resumes at low voltage and relatively low power and again goes up through the DVFS gears to reach top performance. As the application-load diminishes the process is followed in reverse until the equipment is once again idling at the lowest DVFS point on the "little" core.
However, as we have ridden Moore's Law down to smaller dimensions we have also reduced the voltage ranges and thereby reduced DVFS scalability. So ARM's bright idea was to buy back some DVFS trade-off with additional silicon real-estate.
But if we follow Moore's Law on to 20-nm bulk CMOS and 16/14-nm FinFET processes voltage scalability is likely to be yet more reduced, reducing the scope for the use of DVFS within big-little. So what's to be done?