News & Analysis
DesignCon: Nvidia's engineering VP wants better design tools
Brian Fuller
1/29/2013 6:10 PM EST
But rather than sketch a dark and gloomy future for IC design, Alben offered seven tips for improving the situation:
- Promote defend your productivity mentality
- Define a long-term direction
- Pick the most important near-term investment(s)
- Ensure every project does something to improve your company's methodology
- Explicitly allocate budget for methodology staffing
- Involve the product engineers
- Keep the lights on by maintaining your old flow while rolling out a new tool flow rather than suddenly cut over.
In addition to trying to adhere to these rules, Alben said Nvidia has had a two-year collaboration with Synopsys and the EDA giant's VCS tool in which they push the enabling GPU simulation within VCS.
In other words, they "take the design under test (DUT) and move that whole simulation over to the GPU, leaving only the test bench simulation side on the CPU side," Alben said.
The technology is a prototype, "but it's gotten to the point where we have everything we need to run our unit RTL verification environments," he said.
Nvidia runs a simulation farm that has NVidia Tesla K10 accelerator cards installed in them, each running two DUTs. It claims that approach speeds simulation by 5 times, he said.
Nvidia also is collaborating with Rocketick on ATPG gate simulations. Rocketick's RocketSim software offloads calculations to a GPU to shrink verification time. Alben said Nvidia is seeing "extremely high speed up on K10 cards of 17.1x." In one case, a gate simulation shrank from 20 days to 16 hours, he added.Related stories:
--DesignCon: Cisco packs silicon photonics on 3-D ICs
--Nvidia chief scientist to EDA: Give us power tools
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daleste
1/29/2013 10:49 PM EST
As our products grow, the simulations to verify them grow exponentially. Fortunately, those new more powerful chips are now running our computers. The only way to keep ahead is to partition the design and simulate smaller blocks first. Once that is done, you can simulate the entire chip using functional models instead of full designs of the blocks. Timing analysis is still the big issue at the end of the design.
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jeremybirch
1/30/2013 10:58 AM EST
1) engineers complain plenty in my experience - but I guess company culture has an effect upon that.
2) they also quite like to fix issues themselves using scripting etc cos they get a fix sooner and some EDA companies are quite slow to respond or just don't care unless big bucks are attached
3) simulation comes and goes as an issue. In the 90s it was a big bottleneck then cycle based sims, formal equivalence checking and STA came in and made them less relevant. Now chips have grown enough to take up the slack again
4) is simulation the best way to find the answer the designer is looking to answer? It was not the best way to check logic timings (STA is better), it was not the best way to check that synthesis had worked (equivalence checking is better). So do some of these sims have a better alternative eg protocol checking, assertion checking, formal methods based upon the intent of the design?
5) simulation is tough to break across processor cores - although this is easier with shared memory than it was with separate chips. Often the solution here is to simulate at a much lower level but that requires a finer granularity of models to check against and that may require a change in the the way the designers and architects work. NVidia used to (in the 90's) run sims against C models - but the C models were quite high level - perhaps they need to split these down a bit to speed stuff up?
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jeremybirch
1/30/2013 11:20 AM EST
reading to the end of the article sounds like Nvidia might be flogging GPU based simulator systems ;)
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Roba66
1/30/2013 12:34 PM EST
He is right. SPICE and HDL simulators are still single-threaded. EDA companies tend to buy the main components and add things onto them, they do not tend to innovate at the basic tool level.
Another issue is interoperability, it would be natural to link SPICE and HDL in a single run with multitasking but nobody will implement it.
Possibly the revenue model is against making the tools run faster since the big players would sell less seats.
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z3ke
1/30/2013 3:10 PM EST
Have you seen http://upverter.com/
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Sebastien Mirolo
1/30/2013 6:56 PM EST
It is possible for a couple people to put together a web application with sign-up, payment processing, etc. in a week-end.
There has not been this kind of leverage and productivity gain coming out of the EDA and IC industries but it is coming.
You just have to look at Upverter(http://upverter.com/) and (shameless self-promotion) Fortylines(http://fortylines.com).
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jeremybirch
1/31/2013 10:13 AM EST
putting designs into the cloud - you would have to be VERY certain no one else was able to get access to your IP
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Sebastien Mirolo
2/4/2013 8:13 PM EST
For verilog tinkerers, putting your design in the cloud is not an issue when the code is already hosted on github. What matters is access to the underlying IT infrastructure, simulation and verification tools at the lowest cost possible.
For IC companies that care a great deal about running local, it is straightforward to deploy any SaaS such as fortylines on a private cloud. We ship openstack-ready VMs in that case.
There is a trade-off between cost/ease-of-use/security that is different for everyone. Building EDA tools as cloud services enables the flexibility required to adapt to every situation.
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przemek
2/7/2013 5:18 PM EST
IP is such a perishable item: 17 years ensured by the original patent system is far too long nowadays; I can't think of many 17-year old technologies in the high-tech area that still stand on their own.
Today, the speed and excellence of execution matter more than proprietary IP, whether trade secret or patented.
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chanj
1/31/2013 1:55 AM EST
Verification and QA are crucial steps to make a good product. I am glad to hear it.
There is no doubt the complexity of multicore would make the verification task a lot harder and the time would be much longer. Tools become very critical to maintain the streamline of the "production line". I'm very interested in learning what steps Synopsys are doing to help the effort.
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Frank Eory
1/31/2013 5:00 PM EST
I chuckled at the notion of "methodology staffing." In the IC development teams I have worked on, methodology improvements are usually tested, proven and adopted during the course of a product development -- and they are sometimes at odds with what the official corporate CAD empire-mandated methodology is supposed to be.
Rarely does one size fit all designs, but it is the nature of corporate CAD empires to roll out a one-size-fits-all methodology (actually two -- one for digital and one for AMS) for all designers to adopt.
A major issue in this love-hate relationship is that chip designers are competent EDA users but not necessarily EDA experts, while methodology teams are made of EDA experts who aren't (usually) chip designers.
Thus, whenever a new tool, script or methodology enhancement is introduced -- especially if it is mandated -- a designer's response is sometimes "tell me again how many tapeouts those guys have done? Yeah, that's what I thought!"
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