It's rife with errors, like where did they get 10 nJ per bit for NAND? And STT needs transistor isolation, that's at least 6F^2. MLC is not even an option with low MR ratio.
Mcp seems a commonly proposed solution for companies which make both dram and flash. Is it possible they're not making enough margin selling them separately? Their financials may indicate so.
I've always felt DRAM and NVM (i.e., Flash) had different applications, almost exclusive of each other. Generally, I don't expect what is buffered in DRAM to be stored directly, nor what has been stored to be directly read into a DRAM buffer.
The placing of Flash on the DIMM is an exciting development, with the potential of greatly improving PC performance. Unfortunately the figures in this article are so bad that it lacks credibility: What is 25M ns? Is that 25ms? Also the figures appear to be scanned in at a low resolution and are very hard to read, especially in the General/PrintView. While this is unfortunately typical of EETimes articles, the author of a post is responsible for his/her own postings. Rick Merritt - please fix your own post, and try to exert your influence to fix this generic problem.
rick.merritt
2/7/2013 6:09 PM EST
Will flash hop on DDR4? What impact will that have for SSDs?
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bberg
2/8/2013 1:39 PM EST
Viking Technology's ArxCis-NV has this same basic architecture for DDR3, and it is on the market now.
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resistion
2/7/2013 8:49 PM EST
There are serious errors in the chart on p. 2 like mlc and cell size for stt.
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resistion
2/8/2013 7:18 AM EST
"..post-DRAM world" Did Micron really use that expression?
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rick.merritt
2/12/2013 1:39 AM EST
It's a Micron foil
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resistion
2/12/2013 9:26 AM EST
It's rife with errors, like where did they get 10 nJ per bit for NAND? And STT needs transistor isolation, that's at least 6F^2. MLC is not even an option with low MR ratio.
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resistion
2/7/2013 8:54 PM EST
Mcp seems a commonly proposed solution for companies which make both dram and flash. Is it possible they're not making enough margin selling them separately? Their financials may indicate so.
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eewiz
2/7/2013 11:30 PM EST
Interesting concept. Helps for an Instant boot in PCs I guess.
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greenpattern
2/8/2013 1:53 AM EST
Looks incompatible with Intel CPUs with integrated memory controllers.
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rick.merritt
2/8/2013 12:36 PM EST
Samsung and Microsoft officially responded: No comment
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resistion
2/8/2013 12:46 PM EST
Micron also working with AgigA on NVDIMM
http://www.xbitlabs.com/news/memory/display/20121114132456_Micron_and_AgigA_to_Develop_Non_Volatile_DIMM_Technology.html
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vshadan
2/8/2013 12:54 PM EST
FLASH requires ERASE and WRITE, Just the WRITE is much longer time than DRAM's WRITE. How is that taken care?
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iniewski
2/9/2013 10:30 AM EST
Memory world is getting to be interesting...
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EFosters
2/9/2013 2:55 PM EST
Sounds similar to what Spansion and Virident tried to do a few years back, but with NOR. EcoRam DIMMs.
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resistion
2/10/2013 11:41 AM EST
I've always felt DRAM and NVM (i.e., Flash) had different applications, almost exclusive of each other. Generally, I don't expect what is buffered in DRAM to be stored directly, nor what has been stored to be directly read into a DRAM buffer.
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dnh
2/11/2013 3:17 PM EST
The placing of Flash on the DIMM is an exciting development, with the potential of greatly improving PC performance.
Unfortunately the figures in this article are so bad that it lacks credibility: What is 25M ns? Is that 25ms?
Also the figures appear to be scanned in at a low resolution and are very hard to read, especially in the General/PrintView.
While this is unfortunately typical of EETimes articles, the author of a post is responsible for his/her own postings.
Rick Merritt - please fix your own post, and try to exert your influence to fix this generic problem.
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rick.merritt
2/12/2013 1:37 AM EST
@dnh I used foils provided by Micron at the largest size we can accommodate (did you note you can "click to enlarge" them?)
Can you provide more specifics on what you would like to see improved?
Also, don't hesitate to email me at rick.merritt@ubm.com
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