SAN FRANCISCO, Calif. – ASML reported incremental progress on extreme ultraviolet lithography which it said will be the best option for making chips starting at the 10 nm node and below. An executive was more cautious about the outlook for 450mm wafers in an industry keynote here.
Using double patterning and other techniques, EUV can make devices at 7 and 3 nm nodes, Martin van den Brink, chief product and technology officer at ASML told EE Times
after a keynote at the International Solid State Circuits Conference
. “I don’t see a fundamental limit with what we have, the question is can we do it economically,” he said.
He also discussed plans for supporting commercial production of 450mm wafers in 2018 with a second generation EUV system. While Intel, Samsung and TSMC provided additional funding of 828 million euros last year for EUV work, currently Intel is the sole company funding the 450mm program, providing 553 million euros, he said.
“We remain cautious about 450mm [given a] single customer is pushing it,” he said in the keynote.
An EUV prototype at ASML recently delivered up to four billion light pulses at 60W, the equivalent of almost 40 hours operation, he told ISSCC attendees here (see figure below). “This is a major breakthrough and a couple months ago couldn’t have shown it,” he said.
Click on image to enlarge.
He also showed results of EUV at 40W delivering simulated yields of 99.99 percent in five runs of more than an hour, theoretically delivering 165 wafers per hour. “But the issue is we must maintain that” performance, he added.
To make commercial production viable ASML is targeting a goal of making 100 wafers per hour at 250W. In 2014 it hopes to ship a prototype capable of 70 wafers per hour, he said.
ASML is working on a separate EUV problem with mask defects by trying to develop a pellicle for the systems. Today’s immersion lithography systems could be extended to make 10 nm chips with double patterning, but EUV offers a better alternative with single patterning, he argued.
The talk raised questions about the level of investment the industry has placed in a single technology and a single company to continue the pace of chip innovation.Related stories:
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