News & Analysis
ISSCC: ASML says EUV best option at 10nm
Rick Merritt
2/19/2013 3:21 AM EST
SAN FRANCISCO, Calif. – ASML reported incremental progress on extreme ultraviolet lithography which it said will be the best option for making chips starting at the 10 nm node and below. An executive was more cautious about the outlook for 450mm wafers in an industry keynote here.
Using double patterning and other techniques, EUV can make devices at 7 and 3 nm nodes, Martin van den Brink, chief product and technology officer at ASML told EE Times after a keynote at the International Solid State Circuits Conference. “I don’t see a fundamental limit with what we have, the question is can we do it economically,” he said.
He also discussed plans for supporting commercial production of 450mm wafers in 2018 with a second generation EUV system. While Intel, Samsung and TSMC provided additional funding of 828 million euros last year for EUV work, currently Intel is the sole company funding the 450mm program, providing 553 million euros, he said.
“We remain cautious about 450mm [given a] single customer is pushing it,” he said in the keynote.
An EUV prototype at ASML recently delivered up to four billion light pulses at 60W, the equivalent of almost 40 hours operation, he told ISSCC attendees here (see figure below). “This is a major breakthrough and a couple months ago couldn’t have shown it,” he said.
Click on image to enlarge.
He also showed results of EUV at 40W delivering simulated yields of 99.99 percent in five runs of more than an hour, theoretically delivering 165 wafers per hour. “But the issue is we must maintain that” performance, he added.
To make commercial production viable ASML is targeting a goal of making 100 wafers per hour at 250W. In 2014 it hopes to ship a prototype capable of 70 wafers per hour, he said.
ASML is working on a separate EUV problem with mask defects by trying to develop a pellicle for the systems. Today’s immersion lithography systems could be extended to make 10 nm chips with double patterning, but EUV offers a better alternative with single patterning, he argued.
The talk raised questions about the level of investment the industry has placed in a single technology and a single company to continue the pace of chip innovation.
Related stories:
Even with Intel's chips on the table, EUV still no sure bet
Slideshow: IBM outlines fab future beyond FinFETs
Using double patterning and other techniques, EUV can make devices at 7 and 3 nm nodes, Martin van den Brink, chief product and technology officer at ASML told EE Times after a keynote at the International Solid State Circuits Conference. “I don’t see a fundamental limit with what we have, the question is can we do it economically,” he said.
He also discussed plans for supporting commercial production of 450mm wafers in 2018 with a second generation EUV system. While Intel, Samsung and TSMC provided additional funding of 828 million euros last year for EUV work, currently Intel is the sole company funding the 450mm program, providing 553 million euros, he said.
“We remain cautious about 450mm [given a] single customer is pushing it,” he said in the keynote.
An EUV prototype at ASML recently delivered up to four billion light pulses at 60W, the equivalent of almost 40 hours operation, he told ISSCC attendees here (see figure below). “This is a major breakthrough and a couple months ago couldn’t have shown it,” he said.
Click on image to enlarge.
He also showed results of EUV at 40W delivering simulated yields of 99.99 percent in five runs of more than an hour, theoretically delivering 165 wafers per hour. “But the issue is we must maintain that” performance, he added.
To make commercial production viable ASML is targeting a goal of making 100 wafers per hour at 250W. In 2014 it hopes to ship a prototype capable of 70 wafers per hour, he said.
ASML is working on a separate EUV problem with mask defects by trying to develop a pellicle for the systems. Today’s immersion lithography systems could be extended to make 10 nm chips with double patterning, but EUV offers a better alternative with single patterning, he argued.
The talk raised questions about the level of investment the industry has placed in a single technology and a single company to continue the pace of chip innovation.
Related stories:
Even with Intel's chips on the table, EUV still no sure bet
Slideshow: IBM outlines fab future beyond FinFETs
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double-o-nothing
2/19/2013 5:06 AM EST
The 18 nm hp holes show large non-uniformity and the 13 nm hp lines much roughness. The end result is not just ASML's optics, it's also the resist and the mask blank defects. It's also interesting they still need multiple patterning to extend EUV's usability. Also, I'm pretty sure no one uses wire bends anymore at such small scales.
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resistion
2/19/2013 8:30 AM EST
"..no one uses wire bends anymore..."
It's true, layouts would be almost entirely cut lines.
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Alex33
2/19/2013 1:07 PM EST
Not at metal1. Every node a few more restrictions creep in, but it is nothing close to unidirectional. You won't get enough pin placements in the std cells without allowing 2D designs.
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resistion
2/19/2013 8:58 PM EST
Bi-directional M1 is commonly practiced but not necessary. In fact, given EUV's inherent X-Y asymmetry, unidirectional will always be lithographically preferred.
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resistion
2/19/2013 5:14 AM EST
ASML promised 70 WPH @ 15 mJ/cm2, but what if that dose is not enough? What if need 60? They cannot ever be the cost-effective solution.
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greenpattern
2/19/2013 6:37 AM EST
The first slide showed power fluctuations of more than 10% - is that normal?
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kjdsfkjdshfkdshfvc
2/19/2013 9:34 AM EST
Wow, I just learned me something.
http://bit.ly/dI3hcF
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any1
2/19/2013 8:24 PM EST
EUV missed insertion at 14 nm for Intel and I've heard before that Intel thinks 10nm is possible without EUV. Where does that leave TSMC, GLOFO, and Samsung? Will Intel gap them by another node before EUV is ready?
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resistion
2/25/2013 9:10 PM EST
SPIE Keynote from Intel showed EUV out at 10 nm (still in pilot), with only 193 nm extension being used for production at 2H 2015.
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InVT
2/20/2013 11:50 AM EST
I'm guessing if they develop a pellicle process they are going to have to bring it up well above 60W.
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pica
2/21/2013 9:05 AM EST
Any energy consumption estimations?
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de_la_rosa
2/21/2013 11:21 AM EST
I wonder if those resolution results are representative for high throughput conditions.
They are flogging a dead horse!
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Diogenes53
2/21/2013 8:53 PM EST
Bring on angstroms! The horse died when the name was changed from soft x-ray projection lithography to EUV. Who says words don't matter.
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resistion
2/23/2013 5:26 PM EST
Why did they present this at ISSCC? The conference is about circuits and designs, not about devices and processes, don't even mention lithography!
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double-o-nothing
2/23/2013 8:24 PM EST
SPIE Advanced Lithography this week is where the updates on lithography happen.
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resistion
6/13/2013 1:02 AM EDT
The SPIE material is publicly available: http://www.asml.com/doclib/investor/presentations/2013/asml_20130228_EUV_presentation_SPIE_public.pdf
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resistion
6/13/2013 1:24 AM EDT
The 2D feature resolution is still not beating 22 nm and roughness about 15% of that. Photon shot noise is not negligible anymore.
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