News & Analysis
ISSCC: ASML says EUV best option at 10nm
Rick Merritt
2/19/2013 3:21 AM EST
Immersion won't cut it at 10nm, says ASML
Click on image to enlarge.
Click on image to enlarge.
Today's immersion lithography won't be able to economically build 10 nm chips, Van den Brink said, contradicting a position taken last year by an Intel executive.
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double-o-nothing
2/19/2013 5:06 AM EST
The 18 nm hp holes show large non-uniformity and the 13 nm hp lines much roughness. The end result is not just ASML's optics, it's also the resist and the mask blank defects. It's also interesting they still need multiple patterning to extend EUV's usability. Also, I'm pretty sure no one uses wire bends anymore at such small scales.
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resistion
2/19/2013 8:30 AM EST
"..no one uses wire bends anymore..."
It's true, layouts would be almost entirely cut lines.
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Alex33
2/19/2013 1:07 PM EST
Not at metal1. Every node a few more restrictions creep in, but it is nothing close to unidirectional. You won't get enough pin placements in the std cells without allowing 2D designs.
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resistion
2/19/2013 8:58 PM EST
Bi-directional M1 is commonly practiced but not necessary. In fact, given EUV's inherent X-Y asymmetry, unidirectional will always be lithographically preferred.
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resistion
2/19/2013 5:14 AM EST
ASML promised 70 WPH @ 15 mJ/cm2, but what if that dose is not enough? What if need 60? They cannot ever be the cost-effective solution.
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greenpattern
2/19/2013 6:37 AM EST
The first slide showed power fluctuations of more than 10% - is that normal?
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kjdsfkjdshfkdshfvc
2/19/2013 9:34 AM EST
Wow, I just learned me something.
http://bit.ly/dI3hcF
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any1
2/19/2013 8:24 PM EST
EUV missed insertion at 14 nm for Intel and I've heard before that Intel thinks 10nm is possible without EUV. Where does that leave TSMC, GLOFO, and Samsung? Will Intel gap them by another node before EUV is ready?
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resistion
2/25/2013 9:10 PM EST
SPIE Keynote from Intel showed EUV out at 10 nm (still in pilot), with only 193 nm extension being used for production at 2H 2015.
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InVT
2/20/2013 11:50 AM EST
I'm guessing if they develop a pellicle process they are going to have to bring it up well above 60W.
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pica
2/21/2013 9:05 AM EST
Any energy consumption estimations?
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de_la_rosa
2/21/2013 11:21 AM EST
I wonder if those resolution results are representative for high throughput conditions.
They are flogging a dead horse!
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Diogenes53
2/21/2013 8:53 PM EST
Bring on angstroms! The horse died when the name was changed from soft x-ray projection lithography to EUV. Who says words don't matter.
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resistion
2/23/2013 5:26 PM EST
Why did they present this at ISSCC? The conference is about circuits and designs, not about devices and processes, don't even mention lithography!
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double-o-nothing
2/23/2013 8:24 PM EST
SPIE Advanced Lithography this week is where the updates on lithography happen.
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