London Calling: FDSOI clocks at 3GHz

STMicroelectronics is keeping the pot boiling for its fully-depleted silicon-on-insulator (FDSOI) manufacturing process. The latest piece of information shared is that the 28-nm version of the process has produced application processor "engines" capable of being operated at clock frequencies in excess of 3GHz.

ST has not mde clear what the difference between an engine and a processor is, or what extremes of operating temperature were tolerated to achieve the 3-GHz.

For reference the NovaThor L8580 LTE-capable application processor from ST-Ericsson has been benchmarked at operating at up to 2.5-GHz clock frequency at peak performance, but also capable of operating down at 0.6-V to conserve power. So it might be reasonable to infer that ST is saying the L8580 and processors like it could be pushed to beyond 3-GHz if the developers so desired.

The FDSOI planar process, which for now remains a minority interest being promoted by ST, is claimed to have advantages over other more mainstream manufacturing process variants, such as bulk planar CMOS and FinFET CMOS in terms of trade-offs between performance, power consumption and manufacturability.

The use of back baising of silicon beneath the oxide insulator theoretically allows additional high-end performance and the SOI process can also produce operational circuits at lower voltages than alternative processes, proponents claim.  

ST has previously claimed that at 28-nm, its FDSOI process can provide 30 percent more performance than bulk 28-nm CMOS at the same power consumption, or, alternatively, can provide as much as a 50 percent saving in dynamic power consumption at the same performance. That claim may be increased as the company pushes out the top-end performance.

"As we had anticipated, FDSOI is proving to be fast, simple and cool; we had fully expected to see 3GHz operating speeds, the design approach is very consistent with what we had been doing in bulk CMOS, and, with the benefits of fully depleted channels and back biasing, the low-power requirements are also meeting our expectations," said Jean-Marc Chery, chief technology and manufacturing officer of STMicroelectronics, in a statement.

ST said it has found the porting of libraries and physical IP from 28-nm bulk CMOS to 28-nm FDSOI to be straightforward. The process of then designing digital circuits with conventional CAD tools has been identical to designing for bulk CMOS, the company said.

ST will be demonstrating the FDSOI technology at the Mobile World Congress in Barcelona from Feb. 25 to 28.


Related links and articles:

ST-Ericsson shows FDSOI smartphone processor

Globalfoundries commits to FDSOI process

ARM rates FDSOI process as 'good technology'