EXTERNAL CONTENT
Interconnect performance: Overcoming the impact of transistor scaling
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The 14-nm node is expected to be an inflection point for the chip industry where copper interconnect resistivity will increase exponentially and may become a limiting factor in chip design. On Dec. 11 in San Francisco, chip equipment supplier Applied Materials is hosting a technical forum to explore the challenge of interconnect technology keeping pace with transistor scaling and 3-D architectures. Critical decisions confront the semiconductor industry including the possibility of replacing copper for interconnect structures. Many issues are emerging on whether new circuit designs and system architectures can address future limitations in interconnect performance. Applied is convening technologists from across the industry, including Intel, TSMC, ARM, IMEC and SRC to discuss what is being done and major challenges being encountered.
Registration for this event is at www.appliedmaterials.com/interconnect-panel.
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