Venice, Florida — Berkeley Design Automation, Inc., announced the availability of the Noise Analysis OptionTM
that handles complex analog and RF circuit, including all analog-to-digital converters (ADCs), phase-locked loops (PLLs), DC:DC converters, frequency synthesizers, and voltage-controlled oscillators (VCOs).
Device noise is insidious to GHz nanometer-scale analog and RF CMOS circuit performance. Until now, it has been either impractical or impossible to perform transistor-level analysis of the impact of device noise for many complex analog and RF circuits including sigma-delta ADCs, video DACs, fractional-N PLLs, frequency synthesizers, and wideband VCOs. Design teams have had to rely on hand calculations, system-level models, or costly silicon measurements. With the introduction of the Noise Analysis Option, Berkeley Design Automation provides transistor-level noise analysis - including analysis of the impact of white and flicker noise - with true SPICE accuracy for every type of circuit. More than a dozen Berkeley Design Automation customers worldwide are already using the tool on production circuits. Leveraging the company Analog FastSPICETM and RF FastSPICETM technology, the Noise Analysis Option is fully compatible with existing flows, and produces SPICE accurate results.
The Noise Analysis Option includes the following functionality:
- High Capacity transient-noise analysis.
- Periodic steady-state (PSS) convergence with up to 50,000 element capacity.
- Periodic noise (pnoise) analysis that has no accuracy/performance tradeoff.
- Oscillator phase noise (oscnoise) analysis that delivers accuracy on autonomous circuits, provides node and device noise contribution, and automatically provides impulse sensitivity function (ISF) information for every node.
The tool reads standard Cadence Spectre® and Synopsys HSPICE® netlists and models. It is fully integrated into Cadence Virtuoso Analog Design Environment and can operate from a command line.