Product Brief
ADI clock ic can synchronise systems to 1-pps GPS
Vanessa Knivett6/16/2009 1:52 PM EDT
The clock distribution section provides four output drivers. Each driver is programmable either as a single differential LVPECL/LVDS (low-voltage positive emitter-coupled logic/low-voltage differential signalling) output or as pairs of single-ended CMOS (complementary metal-oxide semiconductor) outputs. Each of the four outputs has a dedicated 30bit programmable post divider enabling the generation of multiple different output frequencies. An integrated reference clock multiplier allows for system clock references down to 4MHz, while still supporting outputs of up to 450MHz. The AD9548 also includes a digitally-controlled loop filter, as well as manual and automatic holdover circuitry This, ADI claims, continuously generates a low jitter, valid output clock even when some, or all, references have failed.
The AD9548 is available in an 88 lead, LFCSP and operates between -40 and +85oC.
Please note: The above text is the public part of the press release obtained from the manufacturer (with minor modifications). EETimes Europe/ADLE cannot be held responsible for the claims and statements made by the manufacturer.



