Product Brief
Digital ADC IP uses digital library cells, benefits ASICs and FPGAs
Bill Schweber7/20/2010 8:45 AM EDT
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Stellamar
Stellamar uses a revolutionary technology which allows us to achieve higher ...
Dr DSP
Wonder if this uses the technique described in a Lattice write-up: ...
Chandler, AZ—Startup Stellamar LLC has introduced what they call an innovative, digital-cell-based technology for implementing analog/digital converters in standard ASICs and FPGAs. Using their IP, designers can embed a no-missing-code, oversampling ADC yielding 12-bit resolution and 15-kHz bandwidth, suitable for applications such as data logging, voice, medical instruments, and low-frequency sensors.
The digital core needs only an LVDS input cell, a digital output cell and a handful of passive
external components. The vendor claims their approach reduces time to market and risk significantly, while also decreasing cost and silicon footprint by 50%.SNR at 4 kHz is 72 dB and 68 dB at 15 kHz. The IP has been built and evaluated with a Xilinx Spartan FPGA, see figure.—Bill Schweber
For me information: contact: Stellamar LLC
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Dr DSP
7/23/2010 10:02 PM EDT
Wonder if this uses the technique described in a Lattice write-up: http://www.eetimes.com/design/analog-design/4008891/Leveraging-FPGA-and-CPLD-digital-logic-to-implement-analog-to-digital-converters
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Stellamar
8/4/2010 4:37 PM EDT
Stellamar uses a revolutionary technology which allows us to achieve higher resolutions with lower clocks compared to designs based on Lattice’s technique.
Stellamar Marketing
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