The open-specification organizations VMEbus International Trade Association (VITA) and the PCI Industrial Computing Manufacturers Group (PICMG) are dishing up new higher-speed backplane architectures.

These will handle faster applications by using switched-fabric backplane technologies, but these switched serial interconnects place substantial performance demands on backplane designers.

To meet the challenging design requirements of 3.125- Gbit/s and 6.25-Gbit/s signaling and beyond, you'll have to adopt new design methodologies. You'll also have to choose new materials and printed-circuit-board fabrication techniques.

The Main Effort

The main VITA effort, VXS (VMEbus switched serial standard, VITA 41, part of the VME Renaissance), is a Motorola-led initiative. Here's a pictorial illustrating a VITA 41 interconnect.

VXS design starts with a standard VME64x backplane and implements a high-speed fabric by replacing the existing P0 connector with a new high-speed MultiGig seven-row connector, and adding hub slots fully populated with the new connector.

The PICMG effort is the Advanced Telecommunications Computing Architecture (AdvancedTCA; PICMG 3.0), which is a new form-factor and spec led by Intel and Lucent.

It's completely new and uses the high-speed ZD connector in a new 8U x 280-mm form-factor, forgoing any backward compatibility with PICMG's popular CompactPCI.

VXS and AdvancedTCA both support Ethernet, Infiniband, StarFabric, RapidIO and PCI Express, challenging engineers to find ingenious ways to maintain signal quality at a reasonable cost, despite the negative influences of higher layer counts, greater signal densities and complex signal interactions.

Some believe that the challenges met today at 3.125 Gbits/s and 6.25 Gbits/s will re-emerge as copper signaling moves toward 15 Gbits/s and possibly beyond.

The AdvancedTCA specification permits a variety of architectural implementations. Ingenious channel mapping supports a standard AdvancedTCA switch card to support any configuration. A dual-star (redundant hub slots running the fabric) implementation, for example, could be done with cards at either end of the sub-rack, adjacent in Slots 1 and 2, or in the middle of the backplane.

Cutting Losses

Placing hub slots in the center of the backplane reduces the maximum trace length by half. The result is a big improvement in signal quality because dielectric losses and skin effect are nearly halved.

Further, placing hub slots in the middle simplifies connections, permitting the layer-count to drop from 18 layers to only 12 layers. This not only saves cost, but at 3.2-mm, the thinner board has shorter via stubs---and stubs are one of the most significant loss contributors at gigabit data rates.

In a TDR (time domain reflectometry) profile of a stub for a trace situated in the first signal layer, the minimum differential impedance for this layer just below the connector was only 85 ohms. Measurements indicated that the differential impedance the signal sees is 102 ohms. This optimized performance (within ±2%) is the result of careful trace design, laminate choice, and manufacturing control.

Tests With Real Drivers

Tests using passive and active cards with real drivers operating at 3.125-Gbits/s validated the measurements. The measured eye opening of 509-mV leaves plenty of margin as these drivers only require a minimum opening of 200-mV.

In a live system, performance may be better, because the negative effects of the surface-mount-assembly contacts and cables would be eliminated. Measurements and tests both indicate that FR-4 board material can support speeds of over 5-Gbits/s with the AdvancedTCA layout.

But not all layouts are as generous; the new VXS architecture presented a substantially different challenge, namely remaining backward compatible within the existing VME64x backplane layout constraints.

VXS Backplanes

For VXS, the new MultiGig RT P0 connector and hub slots carry the high-speed switch fabrics, while the P1 and P2 connectors will support legacy VME64x cards. This design maintains full backward compatibility while adding high-speed serial-fabric connectivity.

MultiGig RT is a backplane interconnect family that offers levels of flexibility and customization never before seen in the industry.

This printed-circuit based, pin-less, interconnect family is comprised of modular components which can be used in a variety of combinations. The connectors can be combined to provide the density, data throughput, and signal integrity required.

The use of printed circuit wafers in this connector system supports cost-effective sequencing and electrical customization of the connector. Wafers can be manufactured specifically for differential or signal-ended performance and the impedance, propagation delay, and crosstalk of the connector can be altered per your requirements.

This scalable board-to-backplane connector family eliminates the pin field on backplane boards, and reduces an end user's exposure to field failure in card-cage systems. The MultiGig RT connector family is designed specifically for 20.3-mm (0.8 in.) or 25.4-mm (1 in.) card pitch systems.

VITA 41 designers will have the flexibility of using the P2 connector in a payload slot for the parallel VME64x legacy cards, or the P0 connector in the same payload slot for an Infiniband or RapidIO fabric connection. In the future, StarFabric and PCI Express may also be supported.

The existing 2-mm HM P0 connector wouldn't support well any speeds over 1-Gbit/s; the new VXS design uses a seven-row MultiGig RT connector to handle speeds of up to 10 Gbits/s.

However, accomplishing the dense routing on a 0.8-inch pitch with signals at 3.125-Gbits/s, or higher, requires some creativity. Even a midsize 12-slot dual-star VXS backplane configuration forces you to make some difficult choices.

Up To 18 Layers!

Such a backplane requires as many as 18 layers. Avoiding undesirable stubs for upper-layer backplane traces presents two possible options.

One choice would be to have these worst-case vias back-drilled, a costly fabrication process that removes the un-used portion of the plated via structure below the layer at which the signal is terminated. The other choice is to minimize the length of via stubs by picking a laminate with a lower dielectric constant. This allows the 100-ohm differential impedance to be achieved with thinner circuit board layers.

A lower dielectric constant isn't the only characteristic that makes higher-performance board materials attractive. Materials such as Nelco 4000-13SI, Rogers 4350, and Matsushita Megtron 5 also have significantly lower loss-tangent values at these higher frequencies (Nelco 6000-13SI is not available now). The loss-tangent value indicates a material's degree of undesirable interaction with a signal at a given frequency.

Board choices can be difficult to measure, and a close relationship between a laminate supplier and a board fabricator is essential to achieve consistently high yield rates, as well as acceptable long-term MTBF (mean time between failures). There are many good materials, but the best choice will be the one your vendor has already optimized from a processing perspective.

As has been done for AdvancedTCA, placing the hubs centrally for a VXS layout in most dual-star configurations is a good choice. Because of the superior loss-tangent characteristics, lower dielectric-constant and other performance considerations, Bustronic chose a low-loss laminate for its 12-slot dual-star VXS prototype. For other future configurations that are less challenging (smaller slot-counts, single-star configurations, etc.) a standard FR-4 laminate may be sufficient.

Design Challenges

Let's summarize the design challenges. In general terms, three basic constraints will determine how you, as a design engineer, can achieve an interconnect design goal at these higher speeds.

These constraints are: the length of the backplane path, the desired data rate, and how many signals must be packed per inch of circuit board edge.

The requirements for these three will drive your choice of semiconductor technology, board materials, connectors, via construction, and even other more exotic constructions.

Aside from the VITA and PICMG groups that are today implementing specific backplane architectures at 3.125 Gbits/s and 6.25 Gbits/s, there are study groups within the IEEE and within the Optical Internetworking Forum that are addressing design matters for single-channel backplane interconnects capable of data rates up to 10- Gbits/s.

Regardless of the approach taken, the higher data rates in AdvancedTCA, VXS and other designs require creative backplane design approaches.