Synopsys reached the 1 billion mark for embedded memory test solutions

This week the International Test Conference (ITC) is taking place in Anaheim, so we can expect to see lots of announcements in that area. Test and EDA have always been closely related industries and I can remember many years ago when the test companies were eagerly buying up the EDA startups. Well, recently those tides have turned and we see the EDA industry taking the upper hand, especially with greater levels of test going on-chip. Synopsys gives us a good example of that today with their announcement that over 1 billion chips have shipped with their STAR Memory System.

The STAR Memory System is an advanced built-in-self-test (BIST) solution that provides automated pre- and post-silicon memory test, debug and diagnostic capabilities. The automated BIST insertion and advanced repair features reduce design integration time and overall design cost while improving test quality. Coupled with Synopsys' comprehensive synthesis-based test solution, which also includes TetraMAX® ATPG and DFTMAX™ compression for power-aware scan test, DesignWare SerDes IP with built-in self-test and Yield Explorer for yield analysis, the STAR Memory System, when used in conjunction with DFTMAX compression for logic test, further minimizes the impact on design performance, cost and schedule while meeting overall test cost and quality goals.

"The diagnostic capabilities of Synopsys' STAR Memory System gives us the ability to lower our test costs and improve our manufacturing yield," said Dragos Botea, DFT Manager at SandForce, Inc. "We need a robust, yet economical, integrated test and repair solution to achieve our yield targets and strict quality objectives for our solid state drive processors. The STAR Memory System provides us with the ability to achieve these goals and helps us meet our shrinking product development cycle."

The STAR Memory System can be used with repairable or non-repairable embedded memories for any foundry or process node to address a broad range of design requirements. Its performance-optimized architecture combined with automated hierarchical embedded test and repair logic insertion and integration capability gives designers ease-of-use and increased productivity in achieving their performance, power, area and test goals. Designers optimize the trade-off between area and advanced diagnostics without sacrificing performance or manufacturing test quality. In addition, advanced transient error fault tolerance enables SoC designers to efficiently address high field-reliability and safety requirements for mission-critical applications.

For more information and a short demonstration featuring the post-silicon interactive automation capabilities of the DesignWare' STAR Silicon Browser click here.

Brian Bailey – keeping you covered

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