Product Review
KaiSemi offers FPGA-to-ASIC replacement with a *Zero NRE* model
Clive Maxfield9/15/2010 11:57 AM EDT
Comment
OrenBet
As a former employee of Flextronics-Semi, i took part of several successful ...
GalGilat
Using what they describe as "a breakthrough in automated FPGA-to-ASIC conversion," fabless semiconductor company KaiSemi say that they can provide customers with a seamless, full turnkey FPGA-to-ASIC solution and sell fully compatible replacement chips at a fraction of the price.
I had a long chat with KaiSemi CEO Gal Gilat earlier this week, and I must say that I was very impressed with what he told me. Today's announcement is focused on introducing KaiSemi to the world at large (they are already well-known in Israel) – in future articles we will consider the KaiSemi flow in much more detail.
For the moment, we need only note that KaiSemi's proven process uses a unique in-house tool, which performs an automated conversion directly from the original FPGA netlist into a functionally-identical ASIC gate-level netlist. This is a key point – they don’t touch the RTL for the FPGA – instead they take the final ("golden") fully-functional FPGA netlist and work from that. In addition to the programmable logic itself, conversion process also includes all hard IP blocks in the FPGA, such as DSP cores, RAM blocks, PLLs, Clock Managers, and external interfaces (DDR, PCIe, etc.).
Backed by a tier-one fab vendor, KaiSemi's automated conversion utilizes a database of multiple proven standard-cell fab process libraries and standard cores. The wide range of libraries enables the conversion of any type and size of FPGA from any FPGA vendor while providing deep cost optimization during the automated conversion. The resulting ASICs – which are pin-compatible, timing-compatible, and functionally identical to the original FPGAs – consume significantly less power and cost up to 70% less than their FPGA counterparts.
KaiSemi's automated conversion and flow eliminates the need for customer involvement and resources, NRE costs, long lead times, and the risks that are part of traditional FPGA-to-ASIC conversion flows. KaiSemi manages the whole FPGA-to-ASIC process for the customer, from the purchase order through conversion, the ASIC flow, manufacturing, all the way through to the shipment of the ASIC chips. This seamless conversion process – combined with the Zero NRE model – lets the customer order an ASIC chip as if it were an off-the-shelf second-source replacement chip with a relatively short lead-time.
KaiSemi is set to exhibit in Electronica 2010 trade show in Munich, Germany, from November 9th to November 12th in Hall A5, booth #166.
For more information, visit the KaiSemi website (www.kaisemi.com) or email the head of sales and marketing Avi Pinkas (avip@kaisemi.com).
I had a long chat with KaiSemi CEO Gal Gilat earlier this week, and I must say that I was very impressed with what he told me. Today's announcement is focused on introducing KaiSemi to the world at large (they are already well-known in Israel) – in future articles we will consider the KaiSemi flow in much more detail.
For the moment, we need only note that KaiSemi's proven process uses a unique in-house tool, which performs an automated conversion directly from the original FPGA netlist into a functionally-identical ASIC gate-level netlist. This is a key point – they don’t touch the RTL for the FPGA – instead they take the final ("golden") fully-functional FPGA netlist and work from that. In addition to the programmable logic itself, conversion process also includes all hard IP blocks in the FPGA, such as DSP cores, RAM blocks, PLLs, Clock Managers, and external interfaces (DDR, PCIe, etc.).
Backed by a tier-one fab vendor, KaiSemi's automated conversion utilizes a database of multiple proven standard-cell fab process libraries and standard cores. The wide range of libraries enables the conversion of any type and size of FPGA from any FPGA vendor while providing deep cost optimization during the automated conversion. The resulting ASICs – which are pin-compatible, timing-compatible, and functionally identical to the original FPGAs – consume significantly less power and cost up to 70% less than their FPGA counterparts.
KaiSemi's automated conversion and flow eliminates the need for customer involvement and resources, NRE costs, long lead times, and the risks that are part of traditional FPGA-to-ASIC conversion flows. KaiSemi manages the whole FPGA-to-ASIC process for the customer, from the purchase order through conversion, the ASIC flow, manufacturing, all the way through to the shipment of the ASIC chips. This seamless conversion process – combined with the Zero NRE model – lets the customer order an ASIC chip as if it were an off-the-shelf second-source replacement chip with a relatively short lead-time.
KaiSemi is set to exhibit in Electronica 2010 trade show in Munich, Germany, from November 9th to November 12th in Hall A5, booth #166.
For more information, visit the KaiSemi website (www.kaisemi.com) or email the head of sales and marketing Avi Pinkas (avip@kaisemi.com).
|
|
|
|
|
Navigate to related information
Most Popular
Datasheets.com Parts Search
185 million searchable parts
(please enter a part number or hit search to begin)
Browse the technical library
Our technical library houses over 4,000 high-quality sponsored white papers, application notes, reference guides, use cases—all organized by company.
Our technical library houses over 4,000 high-quality sponsored white papers, application notes, reference guides, use cases—all organized by company.
Max the Magnificent
9/15/2010 12:41 PM EDT
I know this all seems easy if you talk quickly and wave your hands around a lot, but talking to the folks at KaiSemi I really think they have a working solution here. If you've undertaken an FPGA-to-ASIC conversion with KaiSemi, please let us know how it went.
Sign in to Reply
JMParlan
9/15/2010 6:09 PM EDT
You can convert much of the functionality of an FPGA into an ASIC, but you can't duplicate the exact I/O characteristics. Plus, it's difficult to make the ASIC software-compatible with the FPGA. So your ASIC probably won't work in your system without a lot of "customer involvement and resources."
Hard and soft IP are major stumbling blocks. Take a PCIe core for example. Is KaiSemi going to reverse-engineer a Xilinx or Altera PCIe core *exactly* including the register set? (A generic PCIe core will not do because it's not software equivalent.) What about SerDes - will KaiSemi have the technology, and can they legally copy it from the FPGA companies? Even small soft IP blocks are a legal problem. For example, I know that Altera will not allow you to port their IP (like the Nios soft CPU) into an ASIC.
Sign in to Reply
GalGilat
9/15/2010 8:37 PM EDT
Need to clear things up - KaiSemi is a real breakthrough leader and I'm glad one raises questions so I will explain how the "magic" is done:
I would like to refer to each wonder and explain how all are being solved by KaiSemi.
Since a comment is limited to 200 chars, please refer to next set of replies for each wonder mentioned.
Sign in to Reply
GalGilat
9/15/2010 8:38 PM EDT
1.
IOs - we don't need to duplicate IOs characteristics, because IO interface are all standards and are all exist, we use a standard replacement IO cores from the proven Fab libs that we're licensed to. we don't invent the wheel, these cores are existed. What we did is opening the door for a conversion like ours to be able to use these existed standard offering.
Sign in to Reply
GalGilat
9/15/2010 8:38 PM EDT
2.
SW-compatible: probably you meant how it is a functional compatible - it is!. Indeed our IP is not simple and was developed with knowledge and vast experience in netlist conversions for 10 years and 500 successful FPGA-to-ASIC conversions, where the whole group originated in what was Flextronics-Semi conversion division. (That was missed on the report). KaiSemi group history is being the FPGA conversion division of, what was, Orbit Semi, then Flex-Semi, then AMI-Semi and was released to be independent on 2008 after the acquisition by On-Semi.
While in Flextronics-Semi we did Gate-array only, we took it to a different level of supporting standard-cell libs provided by the FAB itself, (opening the door) where in this case there is also a huge offering of cores that are usable.
Sign in to Reply
GalGilat
9/15/2010 8:39 PM EDT
3.
PCIe: There is the PCIe phy hard macro and there is the PCIe embedded controller. The PCIe Phy is a standard core and we can use a the Fab's PCIe core since it is on their offering where we, in addition to buying it, need to fit a wrapper. For the embedded controller PCIe - we don't replace in hard, we offer the customer to use the soft version instead. rather more these embedded macros are not been common in large volume products, since they limit product version upgrades, and therefore are not in the positioning of cost reduction for volumes.
Sign in to Reply
GalGilat
9/15/2010 8:39 PM EDT
4.
Serdes: No need to copy it from FPGA (in fact we don't copy nothing what so ever), Serdes is a standard IO interface core which is offered by the FAB lib that we're licensed to. We fit it to the same constraints with a wrapper. As explained we opened the door to be able to use existed 3rd party offering within the conversion.
Sign in to Reply
GalGilat
9/15/2010 8:41 PM EDT
5.
Soft IP: We don't do nothing illegal! For any soft IP we make sure that the customer upgrade his license with the ip vendor to an ASIC license. These legal issues are considered most important to take into account in the legal aspect and expenses.
Regarding Nios, you can license it to an ASIC with additional pay to Altera. Additionally, for cost maters, we can offer 3rd party replacement soft micro-controllers.
...
I would be happy to explain any other wonder you might have.
Sinceerly,
Gal Gilat
galg@kaisemi.com
Sign in to Reply
OrenBet
9/21/2010 4:43 AM EDT
As a former employee of Flextronics-Semi, i took part of several successful conversions. It is a fast and inexpensive method to replace FPGA. The process in Flex required only small customer involvement. It may not be a solution for an high-end GPU, but for a drop-in replacement of FPGA (even high-end FPGA) an excellent alternative to ASIC development.
Sign in to Reply