Synopsys enhances FPGA synthesis – 4X speedup plus team design capabilities

It's no secret that FPGAs just keep on getting bigger, and Bigger, and BIGGER. This is obviously good news in that greater capacity means that designers can do more with them ... but the downside is that it takes longer and longer to actually get things done.

Cast your mind back into the mists of time and consider Virtex-II FPGAs for example. The largest of these little scamps boasted around only 100K logic elements. This is small capacity-wise by today's standards, but at least you could measure the time it took to go from RTL to a bit-file in minutes.

By comparison, Virtex-4 devices boasted around 200K logic elements and it took hours to go from RTL to a bit-file. The Virtex-5 family topped-out at around 330K logic elements and it took a day to go from RTL to a bit-file. Now we have Virtex-6 devices with 760K logic elements that take days to go from RTL to a bit-file.

And soon we'll be faced with next-generation 28-nm FPGAs in the form of Altera's Stratix-V and Xilinx Virtex-7 devices with 1M+ logic elements ... in which case the time taken to go from RTL to a bit-file will be simply too long unless something is done about it...


All of which explains why the folks at Synopsys have just announced a bunch of enhancements to their Synplify Pro and Synplify Premier FPGA synthesis tools as follows:

Up to 4X synthesis runtime improvement
In the previous release of the tools, Synplify Premier's FAST logic synthesis mode could provide a 2X speed improvement over traditional logic synthesis when using a single processor. In this new release, the FAST synthesis mode can now offer a 4X speedup.

Although FAST synthesis does provide reduced Quality-of-Results (QoR), it is extremely useful for "pipe-cleaning" your design and getting the design working on the board quickly. Once everything is up-and-running, you can go back to perform the full-up synthesis run to squeeze the last drops of optimization and performance out of the design.

Furthermore, a new automatic compile-point capability can be used to intelligently partition the design into blocks. This takes advantage of computers with multiple processor cores to provide up to 30% additional speed improvements with automatic parallel timing-driven synthesis execution on different portions of the design. Note that this 30% speedup can be achieved with both standard logic synthesis and FAST logic synthesis; that is, if FAST synthesis provides a 4X speedup over standard synthesis, then the use of automatic compile points will provide an extra 30% runtime speedup on top (hurray!).

Physical synthesis with new global placer for incremental QoR improvements
A new physical synthesis flow within Synplify Premier employs Synopsys' global placer technology to apply performance improvements to an existing placed and routed design. Physical constraints are automatically determined from prior place and route runs. This makes the flow easy to use for logic synthesis users by freeing them from the need to perform complex physical constraint setup.

 
Now I must admit that it took a bit for me to fully wrap my brain around this, but my current understanding is that once you've got a first-pass at a placed and routed design, you can use this new Synplify Global Placement engine to perform incremental optimizations, after which you have to re-run the FPGA vendor's router.

My understanding is that this currently works only with Xilinx FPGAs, but that Altera FPGA support will be coming soon. I also believe that – in this first incarnation – the results when using this new Synplify Global Placement engine are on a par with the results you get when using the FPGA vendor placement engine. This is not to detract from the new engine in any way – sometimes the new engine will do a better job ... and sometimes the vendor engine will "win".

So why is this new engine of interest? Well remember that this is the first time it's seen the light of day. the fact that it's already on a par with the FPGA vendor placement engine that has been honed and fine-tuned over the years is rather impressive. The folks at Synopsys are really good at what they do, and I expect to see this new engine offering substantial advantages as time goes by.

Team-design interface and bottom-up flows allow parallel development
Both the Synplify Premier and Synplify Pro tools incorporate new team-design features for hierarchical project management and concurrent development. [See also the How-To design article: What! How big did you say that FPGA is? (Team-design for FPGAs)]

Design blocks, or previously verified design IP, can be created and shared internally. Floorplanning is not required, making this flow easy to use. Teams can now manage and review their design implementation results and synthesis settings for each block hierarchically. Design team members can take a snapshot of a block and transfer the design files to the team leader for overall integration into the design. Design blocks can be integrated at both the RTL or EDIF levels, saving time, locking in performance and ensuring predictable results.

Comprehensive DesignWare library support for FPGA-based prototyping
In the past, Synplify Premier did not support the full suite of datapath and building block components within DesignWare Library – now it does (except for MacroCells like the 8051 controller).

This means that Synplify Premier users can now synthesize ASIC RTL that instantiates any of the DesignWare Library's components to create FPGA-based prototypes of their ASIC design and achieve performance-optimized results. ASIC and FPGA component support are now synchronized to help ensure the same DesignWare Library component used in the prototype is also used in the ASIC.

New FPGA devIce support
Another interesting snippet of news is that the new release of the design tools includes synthesis support for the SiliconBlue iCE65 mobile FPGA family (existing customers with “all-vendor” configurations get Silicon Blue support at no additional cost).

Furthermore, the tools also support the 28-nm Altera Stratix-V device family with their 1M+ logic elements and 28 Gbps transceivers, which means we can start creating designs for these devices in anticipation of the physical parts becoming available in the not-so-distant future.

Availability
The 2010.09 release of the Synplify Pro and Synplify Premier products is available now and can be obtained directly from Synopsys through SolvNet by existing customers under maintenance. The Synplify FPGA synthesis products are supported on Windows and Linux, 32 and 64-bit platforms.