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Modular FPGA board for extreme hardware-accelerated computing
Clive Maxfield9/30/2010 4:52 PM EDT
Comment
DouglasMotaDiasDSc
What about development tools for reconfigurable computing (high performance ...
kinnar
The specifications says that the name of this board should be Hippo Board. It ...
Those clever chaps and chappesses at Pico Computing have just announced the release of their M-503 M-Series Module. The most powerful and flexible of the M-Series, the M-503 addresses the ever-increasing demands for memory and I/O bandwidth for High Performance Computing (HPC) applications in the bioinformatics, image processing, and signal processing domains.
The M-503 features a Xilinx Virtex-6 LX240T FPGA with two independent banks of DDR3 SODIMM providing 17 GB/s of local memory bandwidth to the FPGA. In addition to the DDR3, there are three independent banks of QDRII SRAM capable of 10.8 GB/s of sustained random access memory bandwidth.
There are two x8 Gen2 PCIe links provided via Xilinx's PCIe endpoint on the Virtex-6. Eighty (80) LVDS and eight (8) GTX transceivers are available via a high speed high density connector to create direct M-503 to M-503 connections or direct access to SSDs, 10GigE and other peripherals. The M-503 will also be available with the Virtex-6 LX365T, LX550T, SX315T or SX475T FPGAs.
An exciting innovation on the M503 is the HIT (Heterogeneous Interconnect Technology). The HIT is a combination of extremely low latency differential IO interfaces (80 pairs at 1.0 Gb/s each) and extremely fast multi-standard serial IO interfaces (8 GTX transceivers at up to 5 Gb/s). Using customizable mezzanine interconnect boards (either passive or active), or customized hi-speed cables, any combination of parallel mass-storage, multi-standard network connectivity, and board-box-rack interconnect topology can be achieved. This HIT extends the reconfigurability native in FPGAs into the entire architecture of data centers, enabling system-level architecture optimization.

Shown here with three M-503 Modules
The folks at Pico say that the introduction of the M-503 module extends the scalability and general-purpose nature of their FPGA cluster products into many more application domains. Used in conjunction with the EX-500 PCIe backplane, Pico is able to "cluster" three M-503s per PCIe slot or in their SC5 SuperCluster, up to 18 M-503s in a 5U Chassis. The first M-503 based SC5 SuperCluster will ship this month to an unidentified launch customer.
Pico Computing will demonstrate its M-503 module at the International Conference for High Performance Computing 2010 (SC10) November 13-19, 2010 in New Orleans, Louisiana.
The M-503 features a Xilinx Virtex-6 LX240T FPGA with two independent banks of DDR3 SODIMM providing 17 GB/s of local memory bandwidth to the FPGA. In addition to the DDR3, there are three independent banks of QDRII SRAM capable of 10.8 GB/s of sustained random access memory bandwidth.
There are two x8 Gen2 PCIe links provided via Xilinx's PCIe endpoint on the Virtex-6. Eighty (80) LVDS and eight (8) GTX transceivers are available via a high speed high density connector to create direct M-503 to M-503 connections or direct access to SSDs, 10GigE and other peripherals. The M-503 will also be available with the Virtex-6 LX365T, LX550T, SX315T or SX475T FPGAs.
An exciting innovation on the M503 is the HIT (Heterogeneous Interconnect Technology). The HIT is a combination of extremely low latency differential IO interfaces (80 pairs at 1.0 Gb/s each) and extremely fast multi-standard serial IO interfaces (8 GTX transceivers at up to 5 Gb/s). Using customizable mezzanine interconnect boards (either passive or active), or customized hi-speed cables, any combination of parallel mass-storage, multi-standard network connectivity, and board-box-rack interconnect topology can be achieved. This HIT extends the reconfigurability native in FPGAs into the entire architecture of data centers, enabling system-level architecture optimization.

Shown here with three M-503 Modules
The folks at Pico say that the introduction of the M-503 module extends the scalability and general-purpose nature of their FPGA cluster products into many more application domains. Used in conjunction with the EX-500 PCIe backplane, Pico is able to "cluster" three M-503s per PCIe slot or in their SC5 SuperCluster, up to 18 M-503s in a 5U Chassis. The first M-503 based SC5 SuperCluster will ship this month to an unidentified launch customer.
Pico Computing will demonstrate its M-503 module at the International Conference for High Performance Computing 2010 (SC10) November 13-19, 2010 in New Orleans, Louisiana.
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Max the Magnificent
9/30/2010 5:15 PM EDT
As soon as you use one of these little scamps for a real-world project, please let me know about it ... maybe we could write an article about it...
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kinnar
10/4/2010 2:53 PM EDT
The specifications says that the name of this board should be Hippo Board. It extraordinary design.
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DouglasMotaDiasDSc
10/7/2010 4:38 PM EDT
What about development tools for reconfigurable computing (high performance computing / algorithm acceleration)? What Pico and/or a third-party offers for M-503?
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