Veridae Systems delivers new debug solution for FPGAs, ASICs, and SoCs

Our ability to verify complex FPGA, ASIC, and SoC designs is an ever-growing concern. Even though we’ve got access to incredibly sophisticated technology like hardware acceleration, emulation, and formal verification … bugs get through anyway.

As the folks at the ITRS (International Technology Roadmap for Semiconductors) say: "Without major breakthroughs, design verification will be a non-scalable, show-stopping barrier to further progress in the semiconductor industry.”

You have to admit that this doesn’t sound as though they are wearing their happy faces, does it? And you can see why if you look at the chart of Escapes shown below, where an “Escape” is defined as a bug that escapes and gets through into the final design (all the way into prototype silicon in the case of an ASIC or SoC). The chart below – which is based on ITRS figures from 2007 where all values are normalized to 2007 refelects Escapes per 100,000 lines of RTL source code.

As we see, even though the Escape Rate (orange line) is falling, the actual number of Escapes (red line) is rising due to the increasing size and complexity of today’s designs. Meanwhile, the Pin Count (green line) is not scaling with the Gate Count (blue line), which reflects the fact that relative visibility into the internals of the device is falling.


The reason I’m waffling on about this is that a new EDA start-up company has just leapt onto the center of the stage with a flurry of trumpets. The guys and gals at Veridae Systems (www.veridae.com) have announced their Clarus Post-Silicon Validation Suite, which they (modestly) describe as: “A breakthrough silicon debug toolkit that provides unprecedented visibility into the operation of complex system on chips (SoCs), field programmable gate arrays (FPGAs), and application specific integrated circuits (ASICs).”


Clarus provides designers with simulation-style visibility into complex device behavior throughout the design cycle, from initial single- and multi-FPGA prototypes through IC production. During pre- and post-silicon development, engineers can quickly pinpoint and understand unexpected behaviors, correct problems, and rapidly move devices into production. As a result, Clarus helps designers to avoid costly re-spins and can reduce the overall development time by 10 to 30 percent.

As my old chum Gary Smith, founder and chief analyst of Gary Smith EDA says: "It's great to see a new company in the silicon debug space.  It's a vital technology and we can use all the help we can get."

The Clarus Toolkit addresses one of the biggest challenges facing IC design engineers today: the combination of complexity and faster operating speeds has created a gap between IC design capability and verification capacity. This verification gap creates costly delays for manufacturers, as fewer than 40% of all designs achieve first-pass success, and up to 25% of designs require a third pass or worse.  Delays due to debug can amount to millions of dollars in development costs and missed market opportunities.

The Clarus post-silicon validation suite solves this problem by giving designers real-time access to thousands of internal state machines and signals, and presenting captured information in a simulation-style format.  Debug problems that previously required weeks, or even months, can be resolved in hours. This substantially reduces the time required between the arrival of initial prototypes and the final production release – a timeframe that typically accounts for up to 50% of the development cycle.


“Clarus will make a significant addition to our customers’ design flow,” said Mike Dini, CEO of The Dini Group. "Until now, there was nothing commercially available that allowed designers to efficiently debug multi-FPGA systems. Clarus promises to change the industry’s expectations for debug and validation, and we look forward to our customers realizing the gains in efficiency when bringing next-generation designs to market.”

Opening the bottleneck in IC design with smarter debug and validation
Veridae’s new debug and validation toolset includes the Clarus Implementor, the Clarus Analyzer, and the Clarus Investigator.  The Clarus Implementor is an easy-to-use tool that quickly analyzes the design RTL, recommends an optimal signal capture infrastructure, and automatically creates the necessary logic for that infrastructure.

The Clarus Analyzer provides an interface to the on-chip infrastructure, similar to the functionality of a logic analyzer.  Resulting waveforms may be viewed in the industry standard VCD format, allowing data to be shared easily between design, validation and verification engineers.  The Clarus Analyzer allows new signal sets to be captured at any time, with no need to re-synthesize the design.

The Clarus Investigator provides designers maximum insight into the captured data, without tedious manual analysis.  The Clarus investigator automatically merges multiple sets of capture data into one coherent view, and relates the information back to the design RTL, identifying all equivalent and implied signals. The Clarus tools provide a consistent user interface and hierarchical usage model, providing a seamless transition between the single- and multi-FPGA ASIC prototype and IC debug process.


“Clarus was developed by IC designers for IC designers,” said Dr. Brad Quinton, chief technology officer of Veridae Systems. “We experienced the significant challenge of validating today’s complex designs and developed a solution that is like having a logic analyzer on chip. By offering unprecedented visibility into device behavior throughout the design process, Clarus takes the guesswork out of silicon debug and allows manufacturers to realize significant savings in both cost and time to market.”

The Clarus Suite is available now.  In addition to the software suite, on-site debug design support services are available.