FPGA Ethernet switch IP cores with HSR (IEC 62439-3) support from Lattice and Flexibilis

Lattice Semiconductor and Flexibilis have announced the immediate availability of the Flexibilis Ethernet Switch (FES) IP cores. The triple speed (10Mbps/100Mbps/1Gbps) FES IP cores operate on Ethernet Layer 2 and can switch with Gigabit forwarding capacity per port.  Both Gigabit Fiber optic and Gigabit twisted pair copper Ethernet interfaces are supported.  Quality of Service is supported with up to four queues per port.  These Ethernet switch IP cores, available in five versions, vary in their number of ports and functionality:

6-port FES – HSR (QuadBox)
4-port FES – HSR (End-node / RedBox)
8-port FES
4-port FES
3-port FES

The FES – HSR IP cores enable designers of smart grid substation automation and industrial networking applications to immediately and confidently apply the emerging High-availability Seamless Redundancy (HSR) protocol using LatticeECP3 FPGAs.  This IEC protocol (IEC62439-3) provides cost effective redundancy with no single point of failure and zero time to recovery in case of failure.  The HSR protocol is typically used in applications where time synchronization is also needed.  Therefore IEEE 1588 Precision Timing Protocol (PTP) end-to-end transparent switch functionality is also included.  The FES – HSR IP cores are applicable across a range of applications that demand high availability, gigabit-class data transfer capacity and sub-microsecond accuracy.  Target applications include smart grid substation automation and networked industrial automation gear, as well as high availability network equipment.


The FES IP cores are equipped with IEEE 1588 version 2 end-to-end transparent switch functionality, which significantly improves the ability to resist the degradation of clock information quality in larger networks.  This ability is critical in meeting the strict clock quality requirements of future mobile cellular network base stations, wireline access, electrical substation and industrial automation and other control and measurement applications. Nanosecond-class accuracy in clock transfer enables backup or replacement of GPS-based synchronization in critical applications.  This feature makes the FES IP cores suitable for applications such as mobile backhaul routers, cell site routers and industrial automation products.

“We are pleased to provide our Flexibilis Ethernet Switch IP to Lattice’s OEM customers,” said Tomi Norolampi, General Manager of Flexibilis Oy.  “We were able to use our expertise with communications and industrial network equipment to provide advanced functionality in a compact implementation.  The LatticeECP3 FPGA provided us the perfect platform to deliver the most value through our IP.”

“Our collaboration with Flexibilis provides our customers with access to a complete system solution, including development boards, enabling them to rapidly deploy compliant Ethernet technology for low cost to high performance applications using LatticeECP3 FPGAs,” said Lalit Merani, Senior Manager of Product Marketing at Lattice Semiconductor. “These system IP cores enable our OEM customers to immediately implement the IEC High-availability Seamless Redundancy draft standard in their designs today, and upgrade their installed base as the standard evolves.”

For pricing or additional technical information, please visit www.flexibilis.com