Product Review
Dual-image sensor stereo camera FPGA-based reference design from Lattice and Aptina
Clive Maxfield1/8/2012 11:22 AM EST
Comment
Dr DSP
Algorithms that combine multiple camera feeds to compute velocity and ...
Ryan Tennill
I got very excited for a moment thinking that someone had come across the design ...
The folks from Lattice Semiconductor, in collaboration with Aptina (a global provider of CMOS imaging solutions), have announced that they will be demonstrating a low-cost, dual-image sensor design at the Consumer Electronics Show (CES) in Las Vegas, January 10-13, 2012. Lattice’s private hospitality meeting suite (Suite #127) will be located in the Las Vegas Hilton, North Hall, 28th Floor (I suggest you take the lift rather than the stairs :-)
The dual image sensor design utilizes two Aptina MT9M024/MT9M034 720P image sensors and combines the image into a single bus on which an ISP (Image Signal Processor) can operate. The output stream can be used to implement 3D stereoscopic video or for other multi-camera applications. The low cost of the solution enables other consumer applications such as automotive black box drive recorders and surround view cameras. The low cost, low power Lattice MachXO2 PLD and a small SDRAM chip implement the necessary logic and frame buffering that allow the two image sensors to be merged into one ISP bus.
Cliff Cheng, Senior Business Development Marketing Manager for Aptina, said, “This is the latest design in which we have collaborated with Lattice Semiconductor. Their use of the HiSPi protocol further expands the markets for our very popular HD WDR sensors that are used in smart camera and 3D depth sensing camera.”
“We are pleased to offer this dual image sensor design, which allows ISP vendors to quickly offer multiple camera solutions for the consumer market,” said Ted Marena, Director of Business Development for Lattice. “By leveraging the Aptina HiSPi (High speed Serial Pixel interface) bus of the MT9M024/MT9M034, we were able to select a smaller I/O package for the Lattice MachXO2 device, which helped lower the cost.”
Visitors to the Lattice suite at CES can see a demonstration of the dual sensor design. Because the MachXO2 device is programmable, many other dual camera implementations are also possible. Visitors will have the opportunity to speak directly with Lattice senior executives and technical specialists about their own design requirements.
To register for a specific time to visit with Lattice and discuss your specific design challenges, email CES@latticesemi.com.
If you found this article to be of interest, visit Programmable Logic Designline where you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
The dual image sensor design utilizes two Aptina MT9M024/MT9M034 720P image sensors and combines the image into a single bus on which an ISP (Image Signal Processor) can operate. The output stream can be used to implement 3D stereoscopic video or for other multi-camera applications. The low cost of the solution enables other consumer applications such as automotive black box drive recorders and surround view cameras. The low cost, low power Lattice MachXO2 PLD and a small SDRAM chip implement the necessary logic and frame buffering that allow the two image sensors to be merged into one ISP bus.
Cliff Cheng, Senior Business Development Marketing Manager for Aptina, said, “This is the latest design in which we have collaborated with Lattice Semiconductor. Their use of the HiSPi protocol further expands the markets for our very popular HD WDR sensors that are used in smart camera and 3D depth sensing camera.”
“We are pleased to offer this dual image sensor design, which allows ISP vendors to quickly offer multiple camera solutions for the consumer market,” said Ted Marena, Director of Business Development for Lattice. “By leveraging the Aptina HiSPi (High speed Serial Pixel interface) bus of the MT9M024/MT9M034, we were able to select a smaller I/O package for the Lattice MachXO2 device, which helped lower the cost.”
Visitors to the Lattice suite at CES can see a demonstration of the dual sensor design. Because the MachXO2 device is programmable, many other dual camera implementations are also possible. Visitors will have the opportunity to speak directly with Lattice senior executives and technical specialists about their own design requirements.
To register for a specific time to visit with Lattice and discuss your specific design challenges, email CES@latticesemi.com.
If you found this article to be of interest, visit Programmable Logic Designline where you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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Ryan Tennill
1/12/2012 1:07 PM EST
I got very excited for a moment thinking that someone had come across the design our company recently finished which is very similar but merges two 14MP sensors which can be accessed through Ethernet or USB and also provides a 1080p scaled output of both images side-by-side....alas I will have to do it myself!
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Dr DSP
1/18/2012 4:30 PM EST
Algorithms that combine multiple camera feeds to compute velocity and acceleration for crash prediction could be useful too. Lots of cool possibilities once you have good data sources.
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