Product Review
Lattice shipping first samples of LatticeECP4 FPGAs
Clive Maxfield6/6/2012 3:41 PM EDT
Comment
Dr DSP
If you have not checked out the new DSP architecture in these devices you should ...
The folks at Lattice Semiconductor have just announced that they've begun shipping the highest density member of their next-generation LatticeECP4 FPGA family to select customers.
They say that their new LatticeECP4 FPGA family offers the richest portfolio of low cost, low power mid-range devices under 200K LUTs, with high performance innovations such as 6G SERDES in low cost packages, powerful DSP blocks and built-in hard IP-based communication blocks.
The highest density device in the family, the LatticeECP4-190, features 183K LUTs, 480 double data rate DSP multipliers (18x18), 5.8 Mbits of memory and twelve 6 Gbps SERDES channels, making it ideally suited for a broad range of cost- and power-sensitive wireless, wireline, video and computing applications. Lattice has released three flip-chip packages for the LatticeECP4-190 (676, 900 and 1152 pins) that are well suited for a wide range of applications.
The LatticeECP4-190 FPGA offers high-speed CPRI and SRIO 2.1 interfaces and double data rate digital signal processing (DSP) blocks for building heterogeneous wireless networks. The LatticeECP4 FPGAs facilitate rapid construction of the latest 3G/4G metro base stations, small cell stations, pico stations, microwave and millimeter-wave backhaul links. The LatticeECP4-190 FPGA also provides wireline access developers with 36 embedded clock and data recovery (CDR) circuits to build high port density switches and routers using innovative low cost, low power FPGAs. The powerful DSP blocks and a growing portfolio of third-party intellectual property cores and reference designs are also enabling video and surveillance camera customers to implement complex algorithms using affordable, mid-range FPGAs.
"With the silicon release of our LatticeECP4-190 devices, our customers can implement even more complex designs for wireless base stations and backhaul, wireline access, video and display applications and still benefit from the device’s low power and economy," said Sean Riley, Lattice Corporate Vice President and General Manager, Infrastructure Business Unit. “The next generation LatticeECP4 FPGA family brings premium features to infrastructure customers while maintaining industry-leading low power and low cost.”
Design environment accelerates development
Select customers have early access to Lattice Diamond 2.0 beta design software and can begin to design and program their new samples immediately. Lattice Diamond design software is the flagship design environment for Lattice FPGA products and provides a complete set of powerful tools, efficient design flows and a user interface that enable designers to more quickly target low power, cost-sensitive FPGA applications.
In addition, Lattice Diamond software continues to provide industry-leading features specifically developed for low cost and low power applications. These include a very accurate power calculator, a pin-based simultaneous switching output noise calculator and proven MAP and PAR FPGA implementation algorithms that help ensure low cost and low power design solutions.
Click Here to learn more about the Lattice Diamond Design Environment.
About the LatticeECP4 FPGA family
The LatticeECP4 FPGA family features low cost, low power mid-range devices with numerous high performance innovations. The family offers standards-compliant multi-protocol 6G SERDES in low cost wire-bond and flip-chip packages, DDR1/2/3 memory interfaces with speeds up to 1066 Mbps and powerful, cascadable DSP blocks that are ideal for high performance RF, baseband and image signal processing.
The LatticeECP4 is the only FPGA family with high throughput, double data rate DSP blocks and up to 36 embedded clock and data recovery (CDR) circuits. The embedded CDRs can be combined with general purpose I/Os (1.25 Gbps LVDS) to implement a large number of serial Gigabit interfaces. The LatticeECP4 FPGAs also feature embedded memory of up to 5.9 Mbits. Logic density varies from 30K LUTs to 190K LUTs with up to 456 user I/O. The LatticeECP4 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireless infrastructure, wireline access equipment, video, imaging and computing applications.
Click Here for more information about the new LatticeECP4 FPGA family
Pricing and availability
The LatticeECP4-190 silicon and Lattice Diamond 2.0 beta software have been released to select customers developing market-leading solutions. Prices for the LatticeECP4-190 device in the 676fcBGA package in 100K unit volumes will start at $60 for delivery in the second half of 2013.
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
They say that their new LatticeECP4 FPGA family offers the richest portfolio of low cost, low power mid-range devices under 200K LUTs, with high performance innovations such as 6G SERDES in low cost packages, powerful DSP blocks and built-in hard IP-based communication blocks.
The highest density device in the family, the LatticeECP4-190, features 183K LUTs, 480 double data rate DSP multipliers (18x18), 5.8 Mbits of memory and twelve 6 Gbps SERDES channels, making it ideally suited for a broad range of cost- and power-sensitive wireless, wireline, video and computing applications. Lattice has released three flip-chip packages for the LatticeECP4-190 (676, 900 and 1152 pins) that are well suited for a wide range of applications.
The LatticeECP4-190 FPGA offers high-speed CPRI and SRIO 2.1 interfaces and double data rate digital signal processing (DSP) blocks for building heterogeneous wireless networks. The LatticeECP4 FPGAs facilitate rapid construction of the latest 3G/4G metro base stations, small cell stations, pico stations, microwave and millimeter-wave backhaul links. The LatticeECP4-190 FPGA also provides wireline access developers with 36 embedded clock and data recovery (CDR) circuits to build high port density switches and routers using innovative low cost, low power FPGAs. The powerful DSP blocks and a growing portfolio of third-party intellectual property cores and reference designs are also enabling video and surveillance camera customers to implement complex algorithms using affordable, mid-range FPGAs.
"With the silicon release of our LatticeECP4-190 devices, our customers can implement even more complex designs for wireless base stations and backhaul, wireline access, video and display applications and still benefit from the device’s low power and economy," said Sean Riley, Lattice Corporate Vice President and General Manager, Infrastructure Business Unit. “The next generation LatticeECP4 FPGA family brings premium features to infrastructure customers while maintaining industry-leading low power and low cost.”
Design environment accelerates development
Select customers have early access to Lattice Diamond 2.0 beta design software and can begin to design and program their new samples immediately. Lattice Diamond design software is the flagship design environment for Lattice FPGA products and provides a complete set of powerful tools, efficient design flows and a user interface that enable designers to more quickly target low power, cost-sensitive FPGA applications.
In addition, Lattice Diamond software continues to provide industry-leading features specifically developed for low cost and low power applications. These include a very accurate power calculator, a pin-based simultaneous switching output noise calculator and proven MAP and PAR FPGA implementation algorithms that help ensure low cost and low power design solutions.
Click Here to learn more about the Lattice Diamond Design Environment.
About the LatticeECP4 FPGA family
The LatticeECP4 FPGA family features low cost, low power mid-range devices with numerous high performance innovations. The family offers standards-compliant multi-protocol 6G SERDES in low cost wire-bond and flip-chip packages, DDR1/2/3 memory interfaces with speeds up to 1066 Mbps and powerful, cascadable DSP blocks that are ideal for high performance RF, baseband and image signal processing.
The LatticeECP4 is the only FPGA family with high throughput, double data rate DSP blocks and up to 36 embedded clock and data recovery (CDR) circuits. The embedded CDRs can be combined with general purpose I/Os (1.25 Gbps LVDS) to implement a large number of serial Gigabit interfaces. The LatticeECP4 FPGAs also feature embedded memory of up to 5.9 Mbits. Logic density varies from 30K LUTs to 190K LUTs with up to 456 user I/O. The LatticeECP4 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireless infrastructure, wireline access equipment, video, imaging and computing applications.
Click Here for more information about the new LatticeECP4 FPGA family
Pricing and availability
The LatticeECP4-190 silicon and Lattice Diamond 2.0 beta software have been released to select customers developing market-leading solutions. Prices for the LatticeECP4-190 device in the 676fcBGA package in 100K unit volumes will start at $60 for delivery in the second half of 2013.
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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Dr DSP
6/9/2012 2:36 PM EDT
If you have not checked out the new DSP architecture in these devices you should take a quick look. The muxed front end and pre-adder logic really boosts performance without requiring faster fabric. This is a great trend- more performance and lower power.
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