Product Review
Lattice's programmable Power Manager solutions in SSDs
Clive Maxfield6/11/2012 12:28 PM EDT
Comment
I_B_GREEN
No question was possed just a new solution beyond what your chip does.(at least ...
brianlk
The folks at Lattice Semiconductor have just announced some power management solutions that will greatly simplify and increase the reliability of power failure protection circuitry in Solid State Drives (SSDs).
The power failure protection circuitry prevents data loss in the event of input power failure by using the on-board hold-up capacitor to provide supplemental power during that critical period when the data is fully saved into the Flash memory. These circuits traditionally use either a super capacitor or a tantalum capacitor bank along with a voltage boost converter to store the energy.
The innovative Lattice Power Manager II device simplifies and reduces the cost of power failure protection circuitry by integrating the charging and power switchover circuit of the hold-up capacitor. In the case of tantalum hold-up capacitor applications, it eliminates the need for a voltage boost converter.
“The power failure circuitry implemented using our Power Manager II devices can be used across a wide range of solid state drive architectures,” said Shakeel Peera, Senior Director of Strategic Marketing for Lattice Semiconductor. “These power management ICs can greatly lower system cost and free up board space by reducing the hold-up capacitor size.”
Lattice’s Power Manager II devices enable the integration of super capacitor or tantalum capacitor charging and switchover, hot swap control, power fail interrupt and sequencing.
The Power Manager’s precision voltage monitoring (0.7% accuracy), fast response (48 microseconds) and on-chip CPLD greatly improve the reliability of the power failure protection circuitry in an SSD. Faster system response, voltage doubler, capacitor voltage monitor and control circuitry reduce the amount of capacitance required to provide backup power during power outages.
Additional information about the use of Power Manager II devices in SSD design is available at www.latticesemi.com/SSDPOWER
Software support for Power Manager II
Designs for the Power Manager II devices are implemented using the Lattice PAC-Designer design software tools that are available for download free of charge at www.latticesemi.com/pac-designer
About the Power Manager II family
The programmable Power Manager II family consists of six devices that can monitor and control up to 12 power supplies. Within the family, the low power POWR607 device is ideal for portable SSD architectures, controlling up to six supplies and incorporating two high voltage MOSFET drivers. The POWR1014 and POWR1220 devices are well suited for enterprise or PCIe SSD architectures. The POWR1220 device can manage up to 12 voltages and drive 4 N-Channel MOSFETs for the most demanding SSD architectures. It consists of a programmable threshold, precision differential input comparator block with an accuracy of 0.7%, a 48-macrocell CPLD, programmable hardware timers, a 10-bit analog to digital converter and a trim block for the trimming and margining of supplies.
All Lattice programmable mixed-signal product families are supported by development kits and reference designs that enable fast, easy product development.
Click Here for more information about Power Manager II devices.
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
The power failure protection circuitry prevents data loss in the event of input power failure by using the on-board hold-up capacitor to provide supplemental power during that critical period when the data is fully saved into the Flash memory. These circuits traditionally use either a super capacitor or a tantalum capacitor bank along with a voltage boost converter to store the energy.
The innovative Lattice Power Manager II device simplifies and reduces the cost of power failure protection circuitry by integrating the charging and power switchover circuit of the hold-up capacitor. In the case of tantalum hold-up capacitor applications, it eliminates the need for a voltage boost converter.
“The power failure circuitry implemented using our Power Manager II devices can be used across a wide range of solid state drive architectures,” said Shakeel Peera, Senior Director of Strategic Marketing for Lattice Semiconductor. “These power management ICs can greatly lower system cost and free up board space by reducing the hold-up capacitor size.”
Lattice’s Power Manager II devices enable the integration of super capacitor or tantalum capacitor charging and switchover, hot swap control, power fail interrupt and sequencing.
The Power Manager’s precision voltage monitoring (0.7% accuracy), fast response (48 microseconds) and on-chip CPLD greatly improve the reliability of the power failure protection circuitry in an SSD. Faster system response, voltage doubler, capacitor voltage monitor and control circuitry reduce the amount of capacitance required to provide backup power during power outages.
Additional information about the use of Power Manager II devices in SSD design is available at www.latticesemi.com/SSDPOWER
Software support for Power Manager II
Designs for the Power Manager II devices are implemented using the Lattice PAC-Designer design software tools that are available for download free of charge at www.latticesemi.com/pac-designer
About the Power Manager II family
The programmable Power Manager II family consists of six devices that can monitor and control up to 12 power supplies. Within the family, the low power POWR607 device is ideal for portable SSD architectures, controlling up to six supplies and incorporating two high voltage MOSFET drivers. The POWR1014 and POWR1220 devices are well suited for enterprise or PCIe SSD architectures. The POWR1220 device can manage up to 12 voltages and drive 4 N-Channel MOSFETs for the most demanding SSD architectures. It consists of a programmable threshold, precision differential input comparator block with an accuracy of 0.7%, a 48-macrocell CPLD, programmable hardware timers, a 10-bit analog to digital converter and a trim block for the trimming and margining of supplies.
All Lattice programmable mixed-signal product families are supported by development kits and reference designs that enable fast, easy product development.
Click Here for more information about Power Manager II devices.
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
|
|
|
|
|
Navigate to related information
Most Popular
Datasheets.com Parts Search
185 million searchable parts
(please enter a part number or hit search to begin)
Browse the technical library
Our technical library houses over 4,000 high-quality sponsored white papers, application notes, reference guides, use cases—all organized by company.
Our technical library houses over 4,000 high-quality sponsored white papers, application notes, reference guides, use cases—all organized by company.
I_B_GREEN
6/13/2012 12:02 PM EDT
I designed this in descrete form it is flying on the 787 dreamliner.
Inrush limiting, pulse/EMI rejection, but the design is missing one thing, the fet reference needs to be at the cap input.
Sign in to Reply
brianlk
6/13/2012 3:45 PM EDT
Dear Mr. Green,
Thank you for the feedback. The hot swap get gate is controlled by the on chip charge pump. The charge pump voltage is always higher than capacitor voltage +vgs.
Please,ease let me know if I answered your question --Shyam
Sign in to Reply
I_B_GREEN
6/13/2012 5:04 PM EDT
No question was possed just a new solution beyond what your chip does.(at least in the diagram shown)
You must protect the gate voltage with shunt element, because the voltage created across the series resitor subtracts from the gate voltage pinching off the fet on transients and inrush via current across series resitor with storage cap.
Sign in to Reply