Product Review
Altera’s latest Quartus II FPGA design S/W up to 4X faster
Clive Maxfield6/12/2012 12:57 PM EDT
Comment
gwg123
It is truly amazing how much effort and excellent engineering are required to ...
The folks at Altera have just released the latest version of their industry-proven Quartus II development software, which they describe as "The industry’s number one software in performance and productivity for FPGA design."
Quartus II software version 12.0 provides customers additional productivity and performance advantages, such as up to 4X faster compile times for high-performance 28-nm designs.
Additional upgrades include broadened 28-nm device support, including initial support for Altera’s SoC FPGAs, enhanced Qsys system integration and DSP Builder tools, and improved intellectual property (IP) core offerings. For a complete list of features and devices supported by the Quartus II software v12.0, Click Here.
Industry’s fastest FPGA compile times
Quartus II software v12.0 maintains the industry’s fastest compile times, allowing customers to focus design team resources on innovating their designs while maximizing designer productivity.
Stratix V FPGA users will achieve on average a 35 percent reduction in compile times, while Cyclone V and Arria V FPGAs users will see on average a 25 percent reduction in compile times with this software version, as compared to the company’s previous software release.
Expanded 28-nm FPGA support
Quartus II software v12.0 broadens its support for 28-nm FPGAs, including initial support for Altera’s SoC FPGAs, which feature a hard dual-core ARM Cortex-A9 processor. Customers can select and start designing a wide range of low-cost, mid-range and high-end 28-nm FPGAs. New support includes the following:
Qsys system integration tool adds AXI-3 interface support
Also with this release, Altera is adding support for the ARM AMBA AXI-3 interface in its Qsys system integration tool, giving users the flexibility to connect IP cores and IP sub-systems based on different standard interfaces.
Qsys is the FPGA industry’s first system integration tool based on network-on-a-chip (NoC) technology, delivering users a high-performance interconnect. The tool eases system development by integrating IP functions and IP subsystems using a hierarchical approach. The latest release includes several new ease-of-use features that provide additional automation to system designers and simplifies design reuse. More information on Qsys can be found at www.altera.com/qsys
Additional Features in the Quartus II Design Suite Include:
For additional information on the features of Quartus II software version 12.0, visit www.altera.com/q2whatsnew
“From design planning to compilation to implementation, Altera makes the design process easier with the Quartus II software,” said Vince Hu, vice president of product and corporate marketing at Altera. “With our 12.0 release, customers can take advantage of faster compile times and expanded device support to meet today’s system performance requirements and productivity demands, especially for 28-nm design projects.”
About Quartus II
Altera’s Quartus II software improves FPGA designer productivity by offering a complete design suite of industry-leading tools and features. The design environment enables FPGAs designers to meet aggressive time-to-market goals with leading-edge synthesis and place-and-route algorithms, as well as advanced DSP design and system integration tools, and includes a broad portfolio of pre-verified IP cores. The development suite targets all aspects of the FPGA design process, from design entry, to timing closure to verification.
Pricing and availability
Both the Subscription Edition and the free Web Edition of Quartus II software version 12.0 are now available for download. Altera's software subscription program simplifies obtaining Altera design software by consolidating software products and maintenance charges into one annual subscription payment. Subscribers receive Quartus II software, the ModelSim-Altera Starter edition and a full license to the IP Base Suite, which includes 15 of Altera's most popular IP (DSP and memory) cores. The annual software subscription is $2,995 for a node-locked PC license and is available for purchase at Altera's eStore.
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
Quartus II software version 12.0 provides customers additional productivity and performance advantages, such as up to 4X faster compile times for high-performance 28-nm designs.
Additional upgrades include broadened 28-nm device support, including initial support for Altera’s SoC FPGAs, enhanced Qsys system integration and DSP Builder tools, and improved intellectual property (IP) core offerings. For a complete list of features and devices supported by the Quartus II software v12.0, Click Here.
Industry’s fastest FPGA compile times
Quartus II software v12.0 maintains the industry’s fastest compile times, allowing customers to focus design team resources on innovating their designs while maximizing designer productivity.
Stratix V FPGA users will achieve on average a 35 percent reduction in compile times, while Cyclone V and Arria V FPGAs users will see on average a 25 percent reduction in compile times with this software version, as compared to the company’s previous software release.
Expanded 28-nm FPGA support
Quartus II software v12.0 broadens its support for 28-nm FPGAs, including initial support for Altera’s SoC FPGAs, which feature a hard dual-core ARM Cortex-A9 processor. Customers can select and start designing a wide range of low-cost, mid-range and high-end 28-nm FPGAs. New support includes the following:
- Programming support for Stratix V GX and Stratix V GS production devices (5SGXA7, 5SGXA4, 5SGXA3, and 5SGXA5; 5SGSD5 and 5SGSD4)
- Programming support for Stratix V GT FPGA (5SGTC5)
- Device support for the largest Arria V GT FPGA (5AGTD7 with final pin-out)
- Device support for Cyclone V FPGAs (5CEA7 and 5CGTD7; 5CEA9, 5CGXC9, and 5CGTD9)
- Compilation support for Cyclone V SX SoC FPGA (5CSXFC6D6)
Qsys system integration tool adds AXI-3 interface support
Also with this release, Altera is adding support for the ARM AMBA AXI-3 interface in its Qsys system integration tool, giving users the flexibility to connect IP cores and IP sub-systems based on different standard interfaces.
Qsys is the FPGA industry’s first system integration tool based on network-on-a-chip (NoC) technology, delivering users a high-performance interconnect. The tool eases system development by integrating IP functions and IP subsystems using a hierarchical approach. The latest release includes several new ease-of-use features that provide additional automation to system designers and simplifies design reuse. More information on Qsys can be found at www.altera.com/qsys
Additional Features in the Quartus II Design Suite Include:
- New digital signal processing (DSP) support with DSP Builder v12.0—Communicates with DDR memories from MATLAB via System Console and uses new floating-point functions for improved design productivity and greater DSP efficiency.
- Improved Video and Image Processing (VIP) Suite and Video Interface IP—Eases development of video processing applications through an updated Scaler II MegaCore function with edge-adaptive algorithm and new Avalon-Streaming (Avalon-ST) Video Monitor and Trace System IP cores.
- Enhanced Transceiver Design and Verification—Updated transceiver toolkit support for Arria V FPGAs and support for higher speed transceiver data rates (up to 14.1 Gbps in Stratix V FPGAs).
For additional information on the features of Quartus II software version 12.0, visit www.altera.com/q2whatsnew
“From design planning to compilation to implementation, Altera makes the design process easier with the Quartus II software,” said Vince Hu, vice president of product and corporate marketing at Altera. “With our 12.0 release, customers can take advantage of faster compile times and expanded device support to meet today’s system performance requirements and productivity demands, especially for 28-nm design projects.”
About Quartus II
Altera’s Quartus II software improves FPGA designer productivity by offering a complete design suite of industry-leading tools and features. The design environment enables FPGAs designers to meet aggressive time-to-market goals with leading-edge synthesis and place-and-route algorithms, as well as advanced DSP design and system integration tools, and includes a broad portfolio of pre-verified IP cores. The development suite targets all aspects of the FPGA design process, from design entry, to timing closure to verification.
Pricing and availability
Both the Subscription Edition and the free Web Edition of Quartus II software version 12.0 are now available for download. Altera's software subscription program simplifies obtaining Altera design software by consolidating software products and maintenance charges into one annual subscription payment. Subscribers receive Quartus II software, the ModelSim-Altera Starter edition and a full license to the IP Base Suite, which includes 15 of Altera's most popular IP (DSP and memory) cores. The annual software subscription is $2,995 for a node-locked PC license and is available for purchase at Altera's eStore.
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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gwg123
6/14/2012 9:48 AM EDT
It is truly amazing how much effort and excellent engineering are required to obtain even incremental improvements in compile times for FPGAs. I wonder what is coming next?
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