New HyperLink DSP interface FPGA core from Integre Technologies

Integre Technologies, a leading provider of FPGA engineering services and products, today announced the release of the IP-HyperLink high speed digital signal processor (DSP) interface core for use with both Altera and Xilinx device families.

The Integretek IP-HyperLink FPGA core provides a high-speed extension of the AXI interface over a serial connection between a custom FPGA and Texas Instruments Incorporated’s (TI’s) TMS320C66x multicore DSPs. The Integretek IP-HyperLink core leverages TI’s proven HyperLink technology to ensure compatibility with TI’s KeyStone-based multicore processors. Developers supplementing TI's KeyStone devices with proprietary FPGA implementations will benefit from KeyStone’s HyperLink, a dedicated chip- to- chip interface.

Features of the IP-HyperLink FPGA core include:

• AXI4 compliant Master and Slave interfaces
• Up to 25 Gbps transfer rate (4 lane)
• High Speed, Low-Latency, Point to Point Connection
• Simple packet-based transfer protocol for memory mapped access
• Link Self-Initializes

“The IP-HyperLink FPGA core is the first product in our new line of high speed SERDES I/O core family,” states Fred Rakvica, Integre Managing Partner. “We are excited to offer FPGA designers a high-speed window into TI’s DSP world, not only with the HyperLink core, but also our other complementary core products.”

“Integre’s background in FPGA design and experience with high speed I/O make them the logical choice to bring TI’s HyperLink technology to this market,” said Arnon Friedmann, business manager, multicore processors, TI. “The performance of the IP-HyperLink core makes it an excellent solution for high speed communication with our KeyStone-based multicore DSPs.”
    
The IP-HyperLink core is currently available for customer design-in. For more information on the IP-HyperLink core please contact sales@integretek.com

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