Kane's new Altera Stratix V-based Computational Accelerator

The folks from Kane Computing have announced that the Gidel ProcV PCIe x 8 (Gen3) computational accelerator board is now in production and will be available in September 2012.

The ProceV system is based on Altera’s newest generation Stratix V FPGA device. The ProceV provides massive capacity (up to 952K LEs), and high memory and I/O performance.

Thirty-four 12.5 Gb/s transceivers provide external IOs of up to 389 Gb/s. The combination of high-speed direct communication to the FPGA via PCIe gen 3, CXP, SFP+, and General-Purpose physical layer interface makes the ProceV ideal for low-latency, high performance networking and HPC applications.

A powerful memory scheme, composed of embedded memory with 8 TB/s throughput, 16 GB ECC DDR III and 288 Mb DDR II SRAM, enables the high bandwidth, computation, networking, and unique flexibility required to achieve diverse algorithm architectures.

Using a GiDEL add-on daughtercard, the FPGA device can directly interface with standard protocols such as HDMI, SDI, and Camera Link, as well as with the user's propriety I/O systems. The eight-lane PCIe Gen. 3 interface allows for strong co-processing between a standard PC operating system and this FPGA based accelerator.

Richard White, Managing Director of KCL said “The ProceV is ideal for financial trading, ASIC and SoC prototyping and HPRC (High Performance Reconfigurable Computing). The ProceV gives leading edge performance with reliability, maintainability and a long life cycle.”


A comprehensive high level development environment, ProcDeveloper, is also available. Based on this powerful suite, developed over 15 years, GiDEL has consistently been able to meet unique costumer requirements while allowing for flexibility to accommodate long-term product evolution.

ProcDeveloper inclues ProcWizard, ProcMultiPort, and other IPs; Quartus II, USBBlaster, and optional ProcHILs and TotalHistory.

The ProcWizard performs hardware initialization and automatically generates the following:

• Top-level designs, interface modules/entities and on-board memory controllers for application use.
• Device constraints (e.g., timing, pin-outs and drive strength).
• C++ class(es) application driver(s) enable simultaneous accesses of multiple applications, each to its' dedicated section of the Proc board.
• Interface documentation in HTML or MS Word.

The ProcMultiPort IP and other GiDEL memory control IPs, such as the MegaFIFO IP, provide simple access to the on-board DRAM. The ProcMultiPort splits the memory into several logical memories, each accessible simultaneously by multiple ports. As a result, the onboard memory is mapped according to the desired algorithm and not vice versa. The main benefits are:

• Simplification of design and enhanced system performance.
• Design compatibility and migration amongst legacy and future GiDEL Proc boards.
• Replaces the need for inventory of special memories by using standard memory and IP.

The ProcHILs, based on an intuitive interface, enables developers to use Simulink as a design entry tool to achieve full system performance while the algorithm developer does not need any knowledge of the HDL language. In addition, the ProcHILs using Hardware in the Loop (HIL) methodology to significantly accelerates Simulink simulation by taking advantage of the FPGA’s high performance capabilities. Other high-level design entry options, such as C++, are available via GiDEL’s partners.

GiDEL’s TotalHistory provides virtually unlimited visibility depth to internal signals, taking advantage of unused on-board memory. TotalHistory requires no additional hardware and may work at your customers' site to support remote debugging.

About GiDEL
GiDEL (www.gidel.com) was founded in 1993 as a high-end system development and integration company.  With their project-level approach they created several powerful and advanced tools for high-performance system development.  Their accumulated expertise in system level integration, together with their innovative development methodologies has proved to be valuable to companies that need to verify ASIC designs and to those companies building system-level boards.  In 1997 they began providing their in-house development systems to industry. Today, GiDEL is one of the leading companies providing cost-effective integrated building blocks and production boards to system builders that need fast prototyping in order to cut development time.  To ASIC / SoC/ IP designers GiDEL offers simulation acceleration, real-time emulation and verification tools.

About Kane Computing
KCL (www.kanecomputing.co.uk) has been providing Image Processing, DSP and high performance computing products for use in industry, education and research since 1987 and is a Texas Instruments Third Party Partner specialising in consultancy and advice on TI development tools/platforms and image processing applications. KCL have extensive knowledge and experience of providing video compression solutions for many industries particularly for digital video security and high quality broadcast applications. KCL has a policy of continual improvement and operates its business in accordance with the requirements of ISO9001:2008.

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