Product Review
NI LabVIEW uses HLS to improve FPGA design productivity
Clive Maxfield8/1/2012 4:10 PM EDT
The folks at National Instruments have just sent me the sort of product release I really like … one that's short, sharp, and to the point (grin).
They've announced that their LabVIEW FPGA IP Builder add-on, which uses leading Xilinx Vivado High-Level Synthesis technology to simplify high-performance field-programmable gate array (FPGA) algorithm design. This new LabVIEW add-on enhances productivity by reducing the need for manual optimization of high-performance algorithms. Instead, users specify functional behavior along with design constraints and the software automatically generates a hardware implementation to meet requirements.
The new add-on tightly integrates with LabVIEW and the LabVIEW DSP Design Module, a LabVIEW module that helps researchers and system designers in the RF and telecommunications space quickly create communication links and multirate digital signal processing (DSP) algorithms on FPGAs.
Product Features
Additional resources:
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
They've announced that their LabVIEW FPGA IP Builder add-on, which uses leading Xilinx Vivado High-Level Synthesis technology to simplify high-performance field-programmable gate array (FPGA) algorithm design. This new LabVIEW add-on enhances productivity by reducing the need for manual optimization of high-performance algorithms. Instead, users specify functional behavior along with design constraints and the software automatically generates a hardware implementation to meet requirements.
The new add-on tightly integrates with LabVIEW and the LabVIEW DSP Design Module, a LabVIEW module that helps researchers and system designers in the RF and telecommunications space quickly create communication links and multirate digital signal processing (DSP) algorithms on FPGAs.
Product Features
- Increased FPGA design abstraction for enhanced productivity
- Improved algorithm performance and resource utilization
- Separation of code and design constraints facilitates IP reuse
- Seamless deployment to NI FPGA-based devices and integration with I/O
Additional resources:
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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Dr DSP
8/9/2012 12:19 PM EDT
If you don't know much about the high level design used by LabVIEW it's worth your time to quickly scan the white paper listed at the end of Max's post.
Figure 4 in particular shows how you can easily graphically define a somewhat complex filter and then automatically generate optimized HDL code targeted at a specific FPGA.
These productivity tools are going to be excellent additions to the FPGA bag of tricks. More and more domaine specific tools and IP will soon make it just as easy to design with FPGAs as with MCUs... Even for a chip architect...
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