Product Review
Terasic, Altera FPGA-based boards for high-frequency trading
Clive Maxfield8/9/2012 11:14 AM EDT
To fulfill the design needs that demand high speed, advanced memory interfacing, and the highest logic capacity, Terasic has just announced a host of new FPGA boards for tackling high-bandwidth applications such as high frequency trading, data acquisition, networking, and signal processing.
The boards come in three flavors: the TR5-Lite, which features a conveniently small form-factor; the DE5-NET, which maximizes memory, speed, and bandwidth capabilities; and the TR5-F40W, which promotes flexibility and feature expansion.
The TR5-Lite, a half-length low-profile board, sports dual external 10G SFP+ modules, and memory options including two independent banks of 2GB DDR3 RAM, four independent banks of 32MB QDRII+, high-speed parallel 256MB flash memory, and a SATA port for memory expansion. The slim form-factor package also allows the TR5-Lite to be utilized in stringent server sizes:
The largest Stratix V board is the DE5-NET, which is a superset of the TR5-Lite. Joining the ranks of the Terasic DE series kits, the standard-height 3/4-length DE5-NET includes four SFP+ interfaces, two independent 800MHz DDR3-SODIMM slots, four independent QDRII+ SRAM banks, high-speed 256MB flash, and four SATA ports:
Both the TR5-Lite and DE5-NET boards feature the Stratix V GX FPGA with almost one million logic elements. In addition, integrated transceivers will allow a transfer rate of up to 12.5 Gbps, making the boards fully compliant with version 3.0 of the PCI Express standard, generation 3 of SATA, as well as allowing ultra-low-latency, straight connections to 10G SFP+ modules.
For customers looking for a smaller FPGA density and more flexibility, the TR5-F40W is also available. At standard-height and half-length, the TR5-F40W features a Stratix V GX FPGA with 340K logic elements, high-speed PCIe communication, four SFP+ communication ports, SATA ports and an expandable HSMC port:
“As future high frequency trading and networking applications are leaning towards utilizing FPGAs with high-bandwidth memory architectures, Terasic aims to leverage its proximity to high-quality manufacturers to deliver cost-competitive state-of-the-art solutions for today’s high performance computing and finance industry,” states Terasic CEO Sean Peng.
Please visit: http://stratix5.terasic.com for a complete guide on all Terasic's Stratix V boards.
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
The boards come in three flavors: the TR5-Lite, which features a conveniently small form-factor; the DE5-NET, which maximizes memory, speed, and bandwidth capabilities; and the TR5-F40W, which promotes flexibility and feature expansion.
The TR5-Lite, a half-length low-profile board, sports dual external 10G SFP+ modules, and memory options including two independent banks of 2GB DDR3 RAM, four independent banks of 32MB QDRII+, high-speed parallel 256MB flash memory, and a SATA port for memory expansion. The slim form-factor package also allows the TR5-Lite to be utilized in stringent server sizes:
The largest Stratix V board is the DE5-NET, which is a superset of the TR5-Lite. Joining the ranks of the Terasic DE series kits, the standard-height 3/4-length DE5-NET includes four SFP+ interfaces, two independent 800MHz DDR3-SODIMM slots, four independent QDRII+ SRAM banks, high-speed 256MB flash, and four SATA ports:
Both the TR5-Lite and DE5-NET boards feature the Stratix V GX FPGA with almost one million logic elements. In addition, integrated transceivers will allow a transfer rate of up to 12.5 Gbps, making the boards fully compliant with version 3.0 of the PCI Express standard, generation 3 of SATA, as well as allowing ultra-low-latency, straight connections to 10G SFP+ modules.
For customers looking for a smaller FPGA density and more flexibility, the TR5-F40W is also available. At standard-height and half-length, the TR5-F40W features a Stratix V GX FPGA with 340K logic elements, high-speed PCIe communication, four SFP+ communication ports, SATA ports and an expandable HSMC port:
“As future high frequency trading and networking applications are leaning towards utilizing FPGAs with high-bandwidth memory architectures, Terasic aims to leverage its proximity to high-quality manufacturers to deliver cost-competitive state-of-the-art solutions for today’s high performance computing and finance industry,” states Terasic CEO Sean Peng.
Please visit: http://stratix5.terasic.com for a complete guide on all Terasic's Stratix V boards.
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
|
|
|
|
|
Navigate to related information
Most Popular
Datasheets.com Parts Search
185 million searchable parts
(please enter a part number or hit search to begin)
Browse the technical library
Our technical library houses over 4,000 high-quality sponsored white papers, application notes, reference guides, use cases—all organized by company.
Our technical library houses over 4,000 high-quality sponsored white papers, application notes, reference guides, use cases—all organized by company.
Dr DSP
8/21/2012 7:02 PM EDT
When I was looking at the details of financial number crunching applications on FPGAs the limiting factor always seemed to be the memory interface. Going on and off chip for big chunks of memory to feed the calculation engines was an issue. If the memory access was predictable (like an FFT) you could always pipeline things, but financial calculations required indirections and the resulting additional access time was a killer. Maybe new algorithms are available now to minimize this effect. Anyone out there have an update (or is it too secret to tell..).
Sign in to Reply