Product Review
New MathWorks / Altera webinar heading our way!
Clive Maxfield10/3/2012 2:44 PM EDT
As you may recall, last year the folks from MathWorks hosted two joint webinars with Altera on topics related to FPGA design.
Well, I was excited to hear that the little scamps have a new webinar coming up, titled Verifying Altera Floating-Point IP Cores on FPGAs with MATLAB & Simulink.
In this webinar, the guys and gals from MathWorks will we show how to use their HDL Verifier product to verify a rather novel IP core: a Cholesky decomposition, implemented in floating-point using Altera Cyclone IV and Stratix IV devices. This is one of the Altera cores that BDTI evaluated in a study last year.
They say that they will be showcasing the use of their “FPGA-in-the-loop” feature with a series of demos that show designers how to take third-party IP – in this case, from Altera – and to use a system-level testbench in Simulink.
The webinar’s registration page can be found as follows:
mathworks.com/company/events/webinars/wbnr70377.html
I look forward to seeing you there :-)
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
Well, I was excited to hear that the little scamps have a new webinar coming up, titled Verifying Altera Floating-Point IP Cores on FPGAs with MATLAB & Simulink.
In this webinar, the guys and gals from MathWorks will we show how to use their HDL Verifier product to verify a rather novel IP core: a Cholesky decomposition, implemented in floating-point using Altera Cyclone IV and Stratix IV devices. This is one of the Altera cores that BDTI evaluated in a study last year.
They say that they will be showcasing the use of their “FPGA-in-the-loop” feature with a series of demos that show designers how to take third-party IP – in this case, from Altera – and to use a system-level testbench in Simulink.
The webinar’s registration page can be found as follows:
mathworks.com/company/events/webinars/wbnr70377.html
I look forward to seeing you there :-)
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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