Product Review
Impulse's CoDeveloper compiles ANSI C to Altera's Quartus Qsys
Clive Maxfield11/29/2012 3:53 PM EST
I just heard from the folks at Impulse Accelerated Technologies that they have announced the availability of Impulse C and CoDeveloper revision 3.7, which compiles C algorithms to Altera’s Quartus revision 12 Qsys software. This enables software developers to more easily compile C based algorithms for the fastest integration into Altera Stratix and Cyclone FPGAs.
Software developers increasingly use FPGAs to accelerate compute-bound microprocessor algorithms. But they frequently encounter three problems: #1 Most software developers are not familiar with VHDL, Verilog and hardware design in general; #2 most do not fully understand the nature of hardware resources on FPGA no less on an FPGA based development board; and #3 most cannot readily partition code between running on FPGA hardware and running, often over PCIe, on the host processor.
Impulse C 3.7 bridges these gaps by adding an interface between C algorithms and hardware resources that readily integrates within Qsys and Quartus. This lets a software developer refactor microprocessor oriented C into coarse-grained logic, that is easily machine-parallelized into multiple streaming processes. These processes run in FPGA hardware or are partitioned to run native on the host processor, or on available processor cores from Altera. The cross-compiled code remains fully ANSI C compatible so it can be simulated within standard tools such as MS Visual Studio. For cycle-accurate HDL verification, Impulse C also provides a direct export of a test bench to Mentor ModelSim or Aldec Active HDL.
Software developers work within a C development tool such as Visual Studio to offload the microprocessor code via parallelized optimization to FPGA.
Project managers report 50% time savings on first prototype and more than 80% time savings on iterations using the Impulse C tool to Quartus tool flow.
Interested designers can try C to Quartus/Qsys to FPGA free by requesting an evaluation from www.ImpulseC.com. Impulse also provides design services and free design consultations.
About Impulse Accelerated Technologies
Founded 10 years ago, by members of Data I/O’s original ABEL team, Impulse has grown to be the most widely used C-to-FGPA toolset. Users include Honda, NASA, Toshiba, Hitachi and more than a few Wall Street banks. Impulse C also supports research at nearly 100 Universities worldwide.
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
Software developers increasingly use FPGAs to accelerate compute-bound microprocessor algorithms. But they frequently encounter three problems: #1 Most software developers are not familiar with VHDL, Verilog and hardware design in general; #2 most do not fully understand the nature of hardware resources on FPGA no less on an FPGA based development board; and #3 most cannot readily partition code between running on FPGA hardware and running, often over PCIe, on the host processor.
Impulse C 3.7 bridges these gaps by adding an interface between C algorithms and hardware resources that readily integrates within Qsys and Quartus. This lets a software developer refactor microprocessor oriented C into coarse-grained logic, that is easily machine-parallelized into multiple streaming processes. These processes run in FPGA hardware or are partitioned to run native on the host processor, or on available processor cores from Altera. The cross-compiled code remains fully ANSI C compatible so it can be simulated within standard tools such as MS Visual Studio. For cycle-accurate HDL verification, Impulse C also provides a direct export of a test bench to Mentor ModelSim or Aldec Active HDL.
Software developers work within a C development tool such as Visual Studio to offload the microprocessor code via parallelized optimization to FPGA.
Project managers report 50% time savings on first prototype and more than 80% time savings on iterations using the Impulse C tool to Quartus tool flow.
Interested designers can try C to Quartus/Qsys to FPGA free by requesting an evaluation from www.ImpulseC.com. Impulse also provides design services and free design consultations.
About Impulse Accelerated Technologies
Founded 10 years ago, by members of Data I/O’s original ABEL team, Impulse has grown to be the most widely used C-to-FGPA toolset. Users include Honda, NASA, Toshiba, Hitachi and more than a few Wall Street banks. Impulse C also supports research at nearly 100 Universities worldwide.
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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