Product Review
Sonics launches stand-alone memory scheduler IP block
Brian Fuller9/13/2010 6:00 PM EDT
Comment
Dr DSP
Seems like the 'at best' 55% efficiency number is a bit low. Which memory ...
IP vendor Sonics Inc. takes aim at a major subsystem memory bottleneck this week as it introduces MemMax AMP, a stand-alone memory scheduler in a single ip block.
The RTL-block-level solution is designed to help system-on-chip designers break up the nasty subsystem fist fights that break out with increasing use of high-definition video.
Key features:
Typically, designs have to balance two competing agendas, that of the CPU, which demands low-latency, and the video stream, which requires high bandwidth in long bursts. Give the CPU priority, and you risk dropping video frames; give the video stream priority, and you hamstring the CPU.
“As you’re balancing the arbitration between those two kinds of traffic and flipping pages and banks in DRAM, things become inefficient," said James Mac Hale, vice president of Asia operations for Sonics.
In this contentious environment, Mac Hale claims memory-subsystem performance can be, at best, 55 percent. The MemMax AMP solution claims to lift bandwidth utilization up to 85 percent in certain designs, he added.
The MemMax AMP IP block features a programmable quality of service (QoS) engine that enables designers to fine-tune the demands of the CPU and the video stream to optimize performance of their memory subsystem.
The block interfaces to popular DDR2, DDR3 and LPDDR controllers and works with the AMBA AXI bus.
Mac Hale describes MemMax AMP as a “relatively small” block with three configurations, ranging from 50,000 gates up to an unspecified ceiling. He claims the block adds “in the region of a couple of cents” of silicon die cost.
This compares with an alternative to boosting memory subsystem performance—adding DRAM chips at $2.50 apiece.
Availability: Now
Price: Depends on design and business factors.
For more information, please visit: http://www.sonicsinc.com/MemMax_AMP.htm
The RTL-block-level solution is designed to help system-on-chip designers break up the nasty subsystem fist fights that break out with increasing use of high-definition video.
Key features:
- Supports silicon frequency of up to 533 MHz (in TSMC 65nm GP libraries)
- Supports Fixed, INCR and WRAP burst types
- Supports 4- or 8-bank DRAM systems
- Dedicated CPU queues for better latency control
- Dynamic priority management among independent queues
- Runtime programmability of QoS modes
Typically, designs have to balance two competing agendas, that of the CPU, which demands low-latency, and the video stream, which requires high bandwidth in long bursts. Give the CPU priority, and you risk dropping video frames; give the video stream priority, and you hamstring the CPU.
“As you’re balancing the arbitration between those two kinds of traffic and flipping pages and banks in DRAM, things become inefficient," said James Mac Hale, vice president of Asia operations for Sonics.
In this contentious environment, Mac Hale claims memory-subsystem performance can be, at best, 55 percent. The MemMax AMP solution claims to lift bandwidth utilization up to 85 percent in certain designs, he added.
Note: Sonics is hosting a webinar with EE Times on managing memory-bandwidth bottlenecks, Thursday, Sept. 23, 2010, at 11 a.m. PDT.
The MemMax AMP IP block features a programmable quality of service (QoS) engine that enables designers to fine-tune the demands of the CPU and the video stream to optimize performance of their memory subsystem.
The block interfaces to popular DDR2, DDR3 and LPDDR controllers and works with the AMBA AXI bus.
Mac Hale describes MemMax AMP as a “relatively small” block with three configurations, ranging from 50,000 gates up to an unspecified ceiling. He claims the block adds “in the region of a couple of cents” of silicon die cost.
This compares with an alternative to boosting memory subsystem performance—adding DRAM chips at $2.50 apiece.
Availability: Now
Price: Depends on design and business factors.
For more information, please visit: http://www.sonicsinc.com/MemMax_AMP.htm
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Dr DSP
9/21/2010 8:59 PM EDT
Seems like the 'at best' 55% efficiency number is a bit low. Which memory controller did this number come from? Most modern controllers can hit much higher efficiencies than that. A comparison vs a good controller (Denali/Cadence or Virage/Synopsys) would, I think, show much better 'at best' performance than 55%.
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