Magma preps Talus IC implementation tool for 20nm

PARIS – Magma Design Automation Inc. has introduced Talus 1.2, a next-generation IC implementation solution that is claimed to feature faster, more advanced routing, timing, extraction technologies to accelerate next generation SoC implementation.

Magma (San Jose, California) said Talus 1.2 enables engineers to implement 1 million to 1.5 million cells per day on large designs of blocks of 2 million to 5 million cells. Talus 1.2 is currently in use for complex 28nm designs and is prepared to tackle the challenge of designing at the 20nm process node and beyond, the company said.

Magma's Talus 1.2 integrates technologies such as the company's MX Router, MX Timer, MX Extractor, Concurrent MMMC optimization, Crosstalk avoidance to deliver five to six times faster turnaround time.

In a discussion with EDA DesignLine, Mark Richards, Senior Technical Marketing Manager, Design Implementation Business Unit, Magma Design Automation, explained: "The ‘MX’ portions are very much new technology and in particular leverage Magma’s Tekton/QCP timer and extractor technology to provide simplified signoff flows and massive runtime improvements over Talus 1.1."

He continued: "The concurrent MMMC was always there in Talus1.1 but the new MX architecture allows for at least 5X the competition in the number of scenarios (combinations of modes and corners) that can be handled in the implementation flow. Crosstalk avoidance was also very much part of the Talus1.1 flow but significant improvements have been made on the convergence of these flows in particular (but not limited) to address the increasing crosstalk challenges at 28nm and beyond."

Richards said Magma has worked with many early adopters to enable them to ready their flows for 28nm or to provide them with the capacity and throughput required to meet their schedules.

More specifically, Talus Vortex has been used on at least 5 tapeouts at 28nm and many top tier customers now have Magma as plan of record (POR) for their production designs at the 28nm node. "The tools can always be improved, and we will continue to strive to improve designer productivity with throughput advances and we continue to ensure the shortest time to market of any tools in this space," Richards commented.