Cadence expands Virtuoso custom/analog flow to boost 20nm productivity

‎PARIS – Cadence Design Systems Inc. (San Jose, Calif.) announced it has enhanced its Virtuoso-based custom/analog flow, delivering productivity boosts across the design flow from initial design specification to final GDSII and for process nodes down to 20 nanometers.

Cadence said the unified custom/analog flow, available immediately, embodies the tenets of the EDA360 vision and delivers on the company's end-to-end approach to Silicon Realization through pervasive design intent, abstraction and convergence. The flow brings a holistic approach to analog, custom digital, RF, silicon/package co-design, and mixed-signal design, implementation and verification.

In a discussion with EE Times, John Stabenow, group director, Custom/Analog Design Management, Cadence Design Systems Inc., declared: "We really are embracing the Silicon Realization strategy internally. This is about bringing down silos between design teams and it is also about bringing down silos in development teams."

Stabenow continued: "Using Virtuoso as a hub is something that customers have been demanding. We have seen a lot of activity below 45nm for analog, which is very difficult to do, and these enhancements are required to help the analog designers at advanced nodes. This release is a lot about trying to shorten or compress the design time to good layout as well as remove variations."

A key element of the flow is the introduction of the Virtuoso Power System. All designs can suffer from reliability concerns caused by IR drop and electro-migration (EM). Stabenow noted that Virtuoso Power System identifies problem segments and highlights them on the users layout.

He commented: "What is key here is that the layout designers can see the results of the run in a way that makes sense to them, which is a layout view. The interactive short locator enhances the ability of layout designers to go find the actual source of the problem and fix it. Customers are reporting double productivity or more in this part of the design phase."


The unified custom/analog flow also offers in-design DFM capabilities integrated within the Virtuoso environment that automatically locate and fix potential DFM violations concurrently during the design process, enabling design teams to confidently address manufacturing variability, Cadence claimed.


Cadence also announces a new waveform viewer that eliminates the need for design teams to buy and integrate a third-party tool.

Stabenow stated: "Virtuoso had a gap in a waveform tool. We had them but they have not been as good as what they needed to be for our customers to stay with that waveform tool. There have been customers who have been outside of Virtuoso."

He added: "This release is the first release of a best-in-class waveform capability. There is a neat piece of differentiation here. We are able to handle very large datasets and allow designers to visualize those moves around the waveform extremely fast."

Among other enhancements is the automated constraint checking.

"In Virtuoso, there are a couple of things that we do for adding constraints," indicated Stabenow. "One of the big concerns of the design community is: How do I apply constraints quickly into my schematic? The first piece of technology we are introducing to help design engineers is the circuit prospector. The matching is not new but the methodology is new, and the enhancement to the tool makes it easier to apply the constraints. What is really new here are the bidirectional constraint update and the verification of constraints."

Also new in this release is the support of CPF, outlined Stabenow. Analog designers can now generate a CPF file necessary to pass the IP over to an integration team to ensure the integration and verification of the analog IP.

Finally, the Virtuoso Accelerated Parallel Simulator's new distributed SPICE capabilities extend designers' productivity for realizing design intent from specification within the Virtuoso Analog Design Environment to foundry-qualified SPICE models.

Asked by EE Times to extract the two main enhancements from today's announcement, Stabenow said there are probably three to highlight: not only the Virtuoso DFM and the Virtuoso Power system but also the parasitic-aware design flow with rapid analog prototyping.